From: Alistair Francis <alistair23@gmail.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: Bin Meng <bin.meng@windriver.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Palmer Dabbelt <palmerdabbelt@google.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <Alistair.Francis@wdc.com>
Subject: Re: [PATCH 02/15] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions
Date: Mon, 15 Jun 2020 09:06:42 -0700 [thread overview]
Message-ID: <CAKmqyKNaoDbbrDzHAzKyw5RzsCbgwWQK4NXkkD5R0SPcOurWGw@mail.gmail.com> (raw)
In-Reply-To: <1591625864-31494-3-git-send-email-bmeng.cn@gmail.com>
On Mon, Jun 8, 2020 at 7:18 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This was done in the virt & sifive_u codes, but opentitan codes were
> missed. Remove the riscv_ prefix of the machine* and soc* functions.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/opentitan.c | 29 ++++++++++++++---------------
> 1 file changed, 14 insertions(+), 15 deletions(-)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index b4fb836..0907a42 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -51,7 +51,7 @@ static const struct MemmapEntry {
> [IBEX_PADCTRL] = { 0x40160000, 0x10000 }
> };
>
> -static void riscv_opentitan_init(MachineState *machine)
> +static void opentitan_board_init(MachineState *machine)
> {
> const struct MemmapEntry *memmap = ibex_memmap;
> OpenTitanState *s = g_new0(OpenTitanState, 1);
> @@ -70,7 +70,6 @@ static void riscv_opentitan_init(MachineState *machine)
> memory_region_add_subregion(sys_mem,
> memmap[IBEX_RAM].base, main_mem);
>
> -
> if (machine->firmware) {
> riscv_load_firmware(machine->firmware, memmap[IBEX_RAM].base, NULL);
> }
> @@ -80,17 +79,17 @@ static void riscv_opentitan_init(MachineState *machine)
> }
> }
>
> -static void riscv_opentitan_machine_init(MachineClass *mc)
> +static void opentitan_machine_init(MachineClass *mc)
> {
> mc->desc = "RISC-V Board compatible with OpenTitan";
> - mc->init = riscv_opentitan_init;
> + mc->init = opentitan_board_init;
> mc->max_cpus = 1;
> mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
> }
>
> -DEFINE_MACHINE("opentitan", riscv_opentitan_machine_init)
> +DEFINE_MACHINE("opentitan", opentitan_machine_init)
>
> -static void riscv_lowrisc_ibex_soc_init(Object *obj)
> +static void lowrisc_ibex_soc_init(Object *obj)
> {
> LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
>
> @@ -99,7 +98,7 @@ static void riscv_lowrisc_ibex_soc_init(Object *obj)
> &error_abort, NULL);
> }
>
> -static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
> +static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
> {
> const struct MemmapEntry *memmap = ibex_memmap;
> MachineState *ms = MACHINE(qdev_get_machine());
> @@ -159,26 +158,26 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
> memmap[IBEX_PADCTRL].base, memmap[IBEX_PADCTRL].size);
> }
>
> -static void riscv_lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
> +static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
>
> - dc->realize = riscv_lowrisc_ibex_soc_realize;
> + dc->realize = lowrisc_ibex_soc_realize;
> /* Reason: Uses serial_hds in realize function, thus can't be used twice */
> dc->user_creatable = false;
> }
>
> -static const TypeInfo riscv_lowrisc_ibex_soc_type_info = {
> +static const TypeInfo lowrisc_ibex_soc_type_info = {
> .name = TYPE_RISCV_IBEX_SOC,
> .parent = TYPE_DEVICE,
> .instance_size = sizeof(LowRISCIbexSoCState),
> - .instance_init = riscv_lowrisc_ibex_soc_init,
> - .class_init = riscv_lowrisc_ibex_soc_class_init,
> + .instance_init = lowrisc_ibex_soc_init,
> + .class_init = lowrisc_ibex_soc_class_init,
> };
>
> -static void riscv_lowrisc_ibex_soc_register_types(void)
> +static void lowrisc_ibex_soc_register_types(void)
> {
> - type_register_static(&riscv_lowrisc_ibex_soc_type_info);
> + type_register_static(&lowrisc_ibex_soc_type_info);
> }
>
> -type_init(riscv_lowrisc_ibex_soc_register_types)
> +type_init(lowrisc_ibex_soc_register_types)
> --
> 2.7.4
>
>
next prev parent reply other threads:[~2020-06-15 16:18 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-08 14:17 [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support Bin Meng
2020-06-08 14:17 ` [PATCH 01/15] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions Bin Meng
2020-06-15 16:05 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 02/15] hw/riscv: opentitan: " Bin Meng
2020-06-15 16:06 ` Alistair Francis [this message]
2020-06-08 14:17 ` [PATCH 03/15] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit Bin Meng
2020-06-15 16:07 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 04/15] hw/riscv: sifive_u: Generate device tree node for OTP Bin Meng
2020-06-15 16:08 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 05/15] hw/riscv: sifive_gpio: Clean up the codes Bin Meng
2020-06-15 16:13 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 06/15] hw/riscv: sifive_gpio: Add a new 'ngpio' property Bin Meng
2020-06-15 16:16 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 07/15] hw/riscv: sifive_u: Hook a GPIO controller Bin Meng
2020-06-15 16:26 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 08/15] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs Bin Meng
2020-06-15 16:28 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 09/15] hw/riscv: sifive_u: Add reset functionality Bin Meng
2020-06-15 16:35 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 10/15] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name Bin Meng
2020-06-15 16:39 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 11/15] hw/riscv: sifive_u: Add a new property msel for MSEL pin state Bin Meng
2020-06-15 16:41 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 12/15] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 Bin Meng
2020-06-15 19:02 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 13/15] hw/riscv: sifive_u: Support different boot source per MSEL pin state Bin Meng
2020-06-15 19:04 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 14/15] hw/riscv: sifive_u: Sort the SoC memmap table entries Bin Meng
2020-06-15 19:04 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 15/15] hw/riscv: sifive_u: Add a dummy DDR memory controller device Bin Meng
2020-06-15 19:20 ` Alistair Francis
2020-06-15 19:31 ` [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support Alistair Francis
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