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Tue, 24 Mar 2026 18:35:55 -0700 (PDT) MIME-Version: 1.0 References: <20260321144554.606417-1-npiggin@gmail.com> <20260321144554.606417-2-npiggin@gmail.com> In-Reply-To: <20260321144554.606417-2-npiggin@gmail.com> From: Alistair Francis Date: Wed, 25 Mar 2026 11:35:27 +1000 X-Gm-Features: AaiRm51VUnGiafeER45DKPozTjuJ70UgEDedOjsaatBgPHHWvmrlvfbhJSz13Vo Message-ID: Subject: Re: [PATCH v3 1/3] target/riscv: Fix IALIGN check in misa write To: Nicholas Piggin Cc: qemu-riscv@nongnu.org, Laurent Vivier , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-devel@nongnu.org, Joel Stanley , Nicholas Joaquin , Ganesh Valliappan Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::b135; envelope-from=alistair23@gmail.com; helo=mail-yx1-xb135.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Sun, Mar 22, 2026 at 12:47=E2=80=AFAM Nicholas Piggin wrote: > > The instruction alignment check for the C extension was inverted. > The new value should be checked for C bit clear (thus increasing > IALIGN). If IALIGN is incompatible, then the write to misa should > be suppressed, not just ignoring the update to the C bit. > > From the ISA: > > Writing misa may increase IALIGN, e.g., by disabling the "C" > extension. If an instruction that would write misa increases IALIGN, > and the subsequent instruction=E2=80=99s address is not IALIGN-bit alig= ned, > the write to misa is suppressed, leaving misa unchanged. > > This was found with a verification test generator based on RiESCUE. > > Reported-by: Nicholas Joaquin > Reported-by: Ganesh Valliappan > Signed-off-by: Nicholas Piggin Reviewed-by: Alistair Francis Alistair > --- > target/riscv/csr.c | 16 ++++- > tests/tcg/riscv64/Makefile.softmmu-target | 5 ++ > tests/tcg/riscv64/misa-ialign.S | 88 +++++++++++++++++++++++ > 3 files changed, 106 insertions(+), 3 deletions(-) > create mode 100644 tests/tcg/riscv64/misa-ialign.S > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 5064483917..91421a2dd8 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -2129,9 +2129,19 @@ static RISCVException write_misa(CPURISCVState *en= v, int csrno, > /* Mask extensions that are not supported by this hart */ > val &=3D env->misa_ext_mask; > > - /* Suppress 'C' if next instruction is not aligned. */ > - if ((val & RVC) && (get_next_pc(env, ra) & 3) !=3D 0) { > - val &=3D ~RVC; > + /* > + * misa writes that increase IALIGN beyond alignment of the next > + * instruction cause the write to misa to be suppressed. Clearing > + * "C" extension increases IALIGN. > + */ > + if (!(val & RVC) && (get_next_pc(env, ra) & 3) !=3D 0) { > + /* > + * If the next instruction is unaligned mod 4 then "C" must be > + * set or this instruction could not be executing, so we know > + * this is is clearing "C" (and not just keeping it clear). > + */ > + g_assert(env->misa_ext & RVC); > + return RISCV_EXCP_NONE; > } > > /* Disable RVG if any of its dependencies are disabled */ > diff --git a/tests/tcg/riscv64/Makefile.softmmu-target b/tests/tcg/riscv6= 4/Makefile.softmmu-target > index eb1ce6504a..f176f87ed0 100644 > --- a/tests/tcg/riscv64/Makefile.softmmu-target > +++ b/tests/tcg/riscv64/Makefile.softmmu-target > @@ -36,5 +36,10 @@ run-plugin-interruptedmemory: interruptedmemory > $(QEMU) -plugin ../plugins/libdiscons.so -d plugin -D $<.pout \ > $(QEMU_OPTS)$<) > > +EXTRA_RUNS +=3D run-misa-ialign > +run-misa-ialign: QEMU_OPTS :=3D -cpu rv64,c=3Dtrue,v=3Dtrue,x-misa-w=3Do= n $(QEMU_OPTS) > +run-misa-ialign: misa-ialign > + $(call run-test, $<, $(QEMU) $(QEMU_OPTS)$<) > + > # We don't currently support the multiarch system tests > undefine MULTIARCH_TESTS > diff --git a/tests/tcg/riscv64/misa-ialign.S b/tests/tcg/riscv64/misa-ial= ign.S > new file mode 100644 > index 0000000000..7f1eb30023 > --- /dev/null > +++ b/tests/tcg/riscv64/misa-ialign.S > @@ -0,0 +1,88 @@ > +/* > + * Test for MISA changing C and related IALIGN alignment cases > + * > + * This test verifies that the "C" extension can be cleared and set in M= ISA, > + * that a branch to 2-byte aligned instructions can be executed when "C"= is > + * enabled, and that a write to MISA which would increase IALIGN and cau= se > + * the next instruction to be unaligned is ignored. > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#define RVC (1 << ('C'-'A')) > +#define RVV (1 << ('V'-'A')) > + > +.option norvc > + .text > + .global _start > +_start: > + lla t0, trap > + csrw mtvec, t0 > + > + csrr t0, misa > + li t1, RVC > + not t1, t1 > + and t0, t0, t1 > + csrw misa, t0 > + csrr t1, misa > + li a0, 2 # fail code > + bne t0, t1, _exit # Could not clear RVC in MISA > + > + li t1, RVC > + or t0, t0, t1 > + csrw misa, t0 > + csrr t1, misa > + li a0, 3 # fail code > + bne t0, t1, _exit # Could not set RVC in MISA > + > + j unalign > +. =3D . + 2 > +unalign: > + > + li t1, RVC > + not t1, t1 > + and t0, t0, t1 > + csrw misa, t0 > + csrr t1, misa > + li a0, 4 # fail code > + beq t0, t1, _exit # Was able to clear RVC in MISA > + > + li t0, (RVC|RVV) > + not t0, t0 > + and t0, t0, t1 > + csrw misa, t0 > + csrr t0, misa > + li a0, 5 # fail code > + bne t0, t1, _exit # MISA write was not ignored (RVV was clear= ed) > + > + j realign > +. =3D . + 2 > +realign: > + > + # Success! > + li a0, 0 > + j _exit > + > +trap: > + # Any trap is a fail code 1 > + li a0, 1 > + > +# Exit code in a0 > +_exit: > + lla a1, semiargs > + li t0, 0x20026 # ADP_Stopped_ApplicationExit > + sd t0, 0(a1) > + sd a0, 8(a1) > + li a0, 0x20 # TARGET_SYS_EXIT_EXTENDED > + > + # Semihosting call sequence > + .balign 16 > + slli zero, zero, 0x1f > + ebreak > + srai zero, zero, 0x7 > + j . > + > + .data > + .balign 16 > +semiargs: > + .space 16 > -- > 2.51.0 > >