* [PATCH v4 1/6] target/riscv: add ssu64xl
2025-01-15 18:43 [PATCH v4 0/6] target/riscv: RVA23 profile support Daniel Henrique Barboza
@ 2025-01-15 18:43 ` Daniel Henrique Barboza
2025-01-30 23:51 ` Alistair Francis
2025-01-15 18:43 ` [PATCH v4 2/6] target/riscv: use RVB in RVA22U64 Daniel Henrique Barboza
` (5 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Daniel Henrique Barboza @ 2025-01-15 18:43 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, ajones, Daniel Henrique Barboza
ssu64xl is defined in RVA22 as:
"sstatus.UXL must be capable of holding the value 2 (i.e., UXLEN=64 must
be supported)."
This is always true in TCG and it's mandatory for RVA23, so claim
support for it.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
target/riscv/cpu.c | 1 +
tests/data/acpi/riscv64/virt/RHCT | Bin 390 -> 398 bytes
2 files changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3d4bd157d2..b187ef2e4b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -213,6 +213,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12),
+ ISA_EXT_DATA_ENTRY(ssu64xl, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(supm, PRIV_VERSION_1_13_0, ext_supm),
ISA_EXT_DATA_ENTRY(svade, PRIV_VERSION_1_11_0, ext_svade),
ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu),
diff --git a/tests/data/acpi/riscv64/virt/RHCT b/tests/data/acpi/riscv64/virt/RHCT
index 695022d56c4ac16607d4c622955ad339fbbfe997..b14ec15e553200760a63aad65586913d31ea2edc 100644
GIT binary patch
delta 48
zcmZo;?qlW(@^B96V`N}pOqj@Jz^cQ@$e^;(o|BQSxYW#~B4@H2qXkC_BLhPoBLf2f
D`wIz-
delta 41
wcmeBUZe!*O@^B7mV`N}poG_8gfK`Q&kwIpoJtyPj07f&87)Az$G)4vn0JA^`U;qFB
--
2.47.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v4 1/6] target/riscv: add ssu64xl
2025-01-15 18:43 ` [PATCH v4 1/6] target/riscv: add ssu64xl Daniel Henrique Barboza
@ 2025-01-30 23:51 ` Alistair Francis
0 siblings, 0 replies; 14+ messages in thread
From: Alistair Francis @ 2025-01-30 23:51 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liwei1518,
zhiwei_liu, palmer, ajones
On Thu, Jan 16, 2025 at 4:45 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> ssu64xl is defined in RVA22 as:
>
> "sstatus.UXL must be capable of holding the value 2 (i.e., UXLEN=64 must
> be supported)."
>
> This is always true in TCG and it's mandatory for RVA23, so claim
> support for it.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 1 +
> tests/data/acpi/riscv64/virt/RHCT | Bin 390 -> 398 bytes
> 2 files changed, 1 insertion(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 3d4bd157d2..b187ef2e4b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -213,6 +213,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
> ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12),
> ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12),
> + ISA_EXT_DATA_ENTRY(ssu64xl, PRIV_VERSION_1_12_0, has_priv_1_12),
> ISA_EXT_DATA_ENTRY(supm, PRIV_VERSION_1_13_0, ext_supm),
> ISA_EXT_DATA_ENTRY(svade, PRIV_VERSION_1_11_0, ext_svade),
> ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu),
> diff --git a/tests/data/acpi/riscv64/virt/RHCT b/tests/data/acpi/riscv64/virt/RHCT
> index 695022d56c4ac16607d4c622955ad339fbbfe997..b14ec15e553200760a63aad65586913d31ea2edc 100644
> GIT binary patch
> delta 48
> zcmZo;?qlW(@^B96V`N}pOqj@Jz^cQ@$e^;(o|BQSxYW#~B4@H2qXkC_BLhPoBLf2f
> D`wIz-
>
> delta 41
> wcmeBUZe!*O@^B7mV`N}poG_8gfK`Q&kwIpoJtyPj07f&87)Az$G)4vn0JA^`U;qFB
>
> --
> 2.47.1
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v4 2/6] target/riscv: use RVB in RVA22U64
2025-01-15 18:43 [PATCH v4 0/6] target/riscv: RVA23 profile support Daniel Henrique Barboza
2025-01-15 18:43 ` [PATCH v4 1/6] target/riscv: add ssu64xl Daniel Henrique Barboza
@ 2025-01-15 18:43 ` Daniel Henrique Barboza
2025-01-30 23:52 ` Alistair Francis
2025-01-15 18:43 ` [PATCH v4 3/6] target/riscv: add profile u_parent and s_parent Daniel Henrique Barboza
` (4 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Daniel Henrique Barboza @ 2025-01-15 18:43 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, ajones, Daniel Henrique Barboza
From the time we added RVA22U64 until now the spec didn't declare 'RVB'
as a dependency, using zba/zbb/zbs instead. Since then the RVA22 spec
[1] added the following in the 'RVA22U64 Mandatory Extensions' section:
"B Bit-manipulation instructions
Note: The B extension comprises the Zba, Zbb, and Zbs extensions. At the
time of RVA22U64's ratification, the B extension had not yet been
defined, and so RVA22U64 explicitly mandated Zba, Zbb, and Zbs instead.
Mandating B is equivalent."
It is also equivalent to QEMU (see riscv_cpu_validate_b() in
target/riscv/tcg/tcg-cpu.c).
Finally, RVA23U64 [2] directly mentions RVB as a mandatory extension,
not citing zba/zbb/zbs.
To make it clear that RVA23U64 will extend RVA22U64 (i.e. RVA22 is a
parent of RVA23), use RVB in RVA22U64 as well.
(bios-tables-test change: RVB added to riscv,isa)
[1] https://github.com/riscv/riscv-profiles/blob/main/src/profiles.adoc#61-rva22u64-profile
[2] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc#rva23u64-profile
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
target/riscv/cpu.c | 2 +-
tests/data/acpi/riscv64/virt/RHCT | Bin 398 -> 400 bytes
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b187ef2e4b..6fb4d5f374 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2351,7 +2351,7 @@ static const PropertyInfo prop_marchid = {
static RISCVCPUProfile RVA22U64 = {
.parent = NULL,
.name = "rva22u64",
- .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVU,
+ .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVB | RVU,
.priv_spec = RISCV_PROFILE_ATTR_UNUSED,
.satp_mode = RISCV_PROFILE_ATTR_UNUSED,
.ext_offsets = {
diff --git a/tests/data/acpi/riscv64/virt/RHCT b/tests/data/acpi/riscv64/virt/RHCT
index b14ec15e553200760a63aad65586913d31ea2edc..13c8025b868051485be5ba62974a22971a07bc6a 100644
GIT binary patch
delta 53
zcmeBUp1{l%<l!7LfsuiM@#{n`13^7TMg~>JqB1j+%-qDZl;ot1UQ&#clNpsc(ij;S
I3K$s}0ARKZK>z>%
delta 52
zcmbQh+{ern<l!9B$H>6Im@tvcKtP9)kwJyAsLaeHGdD3UC3&N_6yxMHMkS6EMh1pF
HMg|4|IwT82
--
2.47.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v4 2/6] target/riscv: use RVB in RVA22U64
2025-01-15 18:43 ` [PATCH v4 2/6] target/riscv: use RVB in RVA22U64 Daniel Henrique Barboza
@ 2025-01-30 23:52 ` Alistair Francis
0 siblings, 0 replies; 14+ messages in thread
From: Alistair Francis @ 2025-01-30 23:52 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liwei1518,
zhiwei_liu, palmer, ajones
On Thu, Jan 16, 2025 at 4:45 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> From the time we added RVA22U64 until now the spec didn't declare 'RVB'
> as a dependency, using zba/zbb/zbs instead. Since then the RVA22 spec
> [1] added the following in the 'RVA22U64 Mandatory Extensions' section:
>
> "B Bit-manipulation instructions
>
> Note: The B extension comprises the Zba, Zbb, and Zbs extensions. At the
> time of RVA22U64's ratification, the B extension had not yet been
> defined, and so RVA22U64 explicitly mandated Zba, Zbb, and Zbs instead.
> Mandating B is equivalent."
>
> It is also equivalent to QEMU (see riscv_cpu_validate_b() in
> target/riscv/tcg/tcg-cpu.c).
>
> Finally, RVA23U64 [2] directly mentions RVB as a mandatory extension,
> not citing zba/zbb/zbs.
>
> To make it clear that RVA23U64 will extend RVA22U64 (i.e. RVA22 is a
> parent of RVA23), use RVB in RVA22U64 as well.
>
> (bios-tables-test change: RVB added to riscv,isa)
>
> [1] https://github.com/riscv/riscv-profiles/blob/main/src/profiles.adoc#61-rva22u64-profile
> [2] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc#rva23u64-profile
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 2 +-
> tests/data/acpi/riscv64/virt/RHCT | Bin 398 -> 400 bytes
> 2 files changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index b187ef2e4b..6fb4d5f374 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2351,7 +2351,7 @@ static const PropertyInfo prop_marchid = {
> static RISCVCPUProfile RVA22U64 = {
> .parent = NULL,
> .name = "rva22u64",
> - .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVU,
> + .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVB | RVU,
> .priv_spec = RISCV_PROFILE_ATTR_UNUSED,
> .satp_mode = RISCV_PROFILE_ATTR_UNUSED,
> .ext_offsets = {
> diff --git a/tests/data/acpi/riscv64/virt/RHCT b/tests/data/acpi/riscv64/virt/RHCT
> index b14ec15e553200760a63aad65586913d31ea2edc..13c8025b868051485be5ba62974a22971a07bc6a 100644
> GIT binary patch
> delta 53
> zcmeBUp1{l%<l!7LfsuiM@#{n`13^7TMg~>JqB1j+%-qDZl;ot1UQ&#clNpsc(ij;S
> I3K$s}0ARKZK>z>%
>
> delta 52
> zcmbQh+{ern<l!9B$H>6Im@tvcKtP9)kwJyAsLaeHGdD3UC3&N_6yxMHMkS6EMh1pF
> HMg|4|IwT82
>
> --
> 2.47.1
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v4 3/6] target/riscv: add profile u_parent and s_parent
2025-01-15 18:43 [PATCH v4 0/6] target/riscv: RVA23 profile support Daniel Henrique Barboza
2025-01-15 18:43 ` [PATCH v4 1/6] target/riscv: add ssu64xl Daniel Henrique Barboza
2025-01-15 18:43 ` [PATCH v4 2/6] target/riscv: use RVB in RVA22U64 Daniel Henrique Barboza
@ 2025-01-15 18:43 ` Daniel Henrique Barboza
2025-01-31 0:06 ` Alistair Francis
2025-01-15 18:43 ` [PATCH v4 4/6] target/riscv: change priv_ver check in validate_profile() Daniel Henrique Barboza
` (3 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Daniel Henrique Barboza @ 2025-01-15 18:43 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, ajones, Daniel Henrique Barboza
The current 'parent' mechanic for profiles allows for one profile to be
a child of a previous/older profile, enabling all its extensions (and
the parent profile itself) and sparing us from tediously listing all
extensions for every profile.
This works fine for u-mode profiles. For s-mode profiles this is not
enough: a s-mode profile extends not only his equivalent u-mode profile
but also the previous s-mode profile. This means, for example, that
RVA23S64 extends both RVA23U64 and RVA22S64.
To fit this usage, rename the existing 'parent' to 'u_parent' and add a
new 's_parent' attribute for profiles. Handle both like we were doing
with the previous 'parent' attribute, i.e. if set, enable it. This
change does nothing for the existing profiles but will make RVA23S64
simpler.
Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
target/riscv/cpu.c | 6 ++++--
target/riscv/cpu.h | 3 ++-
target/riscv/tcg/tcg-cpu.c | 35 ++++++++++++++++++++++++++---------
3 files changed, 32 insertions(+), 12 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6fb4d5f374..e215b1004d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2349,7 +2349,8 @@ static const PropertyInfo prop_marchid = {
* doesn't need to be manually enabled by the profile.
*/
static RISCVCPUProfile RVA22U64 = {
- .parent = NULL,
+ .u_parent = NULL,
+ .s_parent = NULL,
.name = "rva22u64",
.misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVB | RVU,
.priv_spec = RISCV_PROFILE_ATTR_UNUSED,
@@ -2381,7 +2382,8 @@ static RISCVCPUProfile RVA22U64 = {
* The remaining features/extensions comes from RVA22U64.
*/
static RISCVCPUProfile RVA22S64 = {
- .parent = &RVA22U64,
+ .u_parent = &RVA22U64,
+ .s_parent = NULL,
.name = "rva22s64",
.misa_ext = RVS,
.priv_spec = PRIV_VERSION_1_12_0,
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 97713681cb..986131a191 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -81,7 +81,8 @@ const char *riscv_get_misa_ext_description(uint32_t bit);
#define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop)
typedef struct riscv_cpu_profile {
- struct riscv_cpu_profile *parent;
+ struct riscv_cpu_profile *u_parent;
+ struct riscv_cpu_profile *s_parent;
const char *name;
uint32_t misa_ext;
bool enabled;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 48be24bbbe..c060b65fbc 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -713,13 +713,29 @@ static bool riscv_cpu_validate_profile_satp(RISCVCPU *cpu,
}
#endif
+static void riscv_cpu_check_parent_profile(RISCVCPU *cpu,
+ RISCVCPUProfile *profile,
+ RISCVCPUProfile *parent)
+{
+ const char *parent_name;
+ bool parent_enabled;
+
+ if (!profile->enabled || !parent) {
+ return;
+ }
+
+ parent_name = parent->name;
+ parent_enabled = object_property_get_bool(OBJECT(cpu), parent_name, NULL);
+ profile->enabled = parent_enabled;
+}
+
static void riscv_cpu_validate_profile(RISCVCPU *cpu,
RISCVCPUProfile *profile)
{
CPURISCVState *env = &cpu->env;
const char *warn_msg = "Profile %s mandates disabled extension %s";
bool send_warn = profile->user_set && profile->enabled;
- bool parent_enabled, profile_impl = true;
+ bool profile_impl = true;
int i;
#ifndef CONFIG_USER_ONLY
@@ -773,12 +789,8 @@ static void riscv_cpu_validate_profile(RISCVCPU *cpu,
profile->enabled = profile_impl;
- if (profile->parent != NULL) {
- parent_enabled = object_property_get_bool(OBJECT(cpu),
- profile->parent->name,
- NULL);
- profile->enabled = profile->enabled && parent_enabled;
- }
+ riscv_cpu_check_parent_profile(cpu, profile, profile->u_parent);
+ riscv_cpu_check_parent_profile(cpu, profile, profile->s_parent);
}
static void riscv_cpu_validate_profiles(RISCVCPU *cpu)
@@ -1181,8 +1193,13 @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name,
profile->user_set = true;
profile->enabled = value;
- if (profile->parent != NULL) {
- object_property_set_bool(obj, profile->parent->name,
+ if (profile->u_parent != NULL) {
+ object_property_set_bool(obj, profile->u_parent->name,
+ profile->enabled, NULL);
+ }
+
+ if (profile->s_parent != NULL) {
+ object_property_set_bool(obj, profile->s_parent->name,
profile->enabled, NULL);
}
--
2.47.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v4 3/6] target/riscv: add profile u_parent and s_parent
2025-01-15 18:43 ` [PATCH v4 3/6] target/riscv: add profile u_parent and s_parent Daniel Henrique Barboza
@ 2025-01-31 0:06 ` Alistair Francis
0 siblings, 0 replies; 14+ messages in thread
From: Alistair Francis @ 2025-01-31 0:06 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liwei1518,
zhiwei_liu, palmer, ajones
On Thu, Jan 16, 2025 at 4:45 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> The current 'parent' mechanic for profiles allows for one profile to be
> a child of a previous/older profile, enabling all its extensions (and
> the parent profile itself) and sparing us from tediously listing all
> extensions for every profile.
>
> This works fine for u-mode profiles. For s-mode profiles this is not
> enough: a s-mode profile extends not only his equivalent u-mode profile
> but also the previous s-mode profile. This means, for example, that
> RVA23S64 extends both RVA23U64 and RVA22S64.
>
> To fit this usage, rename the existing 'parent' to 'u_parent' and add a
> new 's_parent' attribute for profiles. Handle both like we were doing
> with the previous 'parent' attribute, i.e. if set, enable it. This
> change does nothing for the existing profiles but will make RVA23S64
> simpler.
>
> Suggested-by: Andrew Jones <ajones@ventanamicro.com>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 6 ++++--
> target/riscv/cpu.h | 3 ++-
> target/riscv/tcg/tcg-cpu.c | 35 ++++++++++++++++++++++++++---------
> 3 files changed, 32 insertions(+), 12 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 6fb4d5f374..e215b1004d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2349,7 +2349,8 @@ static const PropertyInfo prop_marchid = {
> * doesn't need to be manually enabled by the profile.
> */
> static RISCVCPUProfile RVA22U64 = {
> - .parent = NULL,
> + .u_parent = NULL,
> + .s_parent = NULL,
> .name = "rva22u64",
> .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVB | RVU,
> .priv_spec = RISCV_PROFILE_ATTR_UNUSED,
> @@ -2381,7 +2382,8 @@ static RISCVCPUProfile RVA22U64 = {
> * The remaining features/extensions comes from RVA22U64.
> */
> static RISCVCPUProfile RVA22S64 = {
> - .parent = &RVA22U64,
> + .u_parent = &RVA22U64,
> + .s_parent = NULL,
> .name = "rva22s64",
> .misa_ext = RVS,
> .priv_spec = PRIV_VERSION_1_12_0,
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 97713681cb..986131a191 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -81,7 +81,8 @@ const char *riscv_get_misa_ext_description(uint32_t bit);
> #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop)
>
> typedef struct riscv_cpu_profile {
> - struct riscv_cpu_profile *parent;
> + struct riscv_cpu_profile *u_parent;
> + struct riscv_cpu_profile *s_parent;
> const char *name;
> uint32_t misa_ext;
> bool enabled;
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 48be24bbbe..c060b65fbc 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -713,13 +713,29 @@ static bool riscv_cpu_validate_profile_satp(RISCVCPU *cpu,
> }
> #endif
>
> +static void riscv_cpu_check_parent_profile(RISCVCPU *cpu,
> + RISCVCPUProfile *profile,
> + RISCVCPUProfile *parent)
> +{
> + const char *parent_name;
> + bool parent_enabled;
> +
> + if (!profile->enabled || !parent) {
> + return;
> + }
> +
> + parent_name = parent->name;
> + parent_enabled = object_property_get_bool(OBJECT(cpu), parent_name, NULL);
> + profile->enabled = parent_enabled;
> +}
> +
> static void riscv_cpu_validate_profile(RISCVCPU *cpu,
> RISCVCPUProfile *profile)
> {
> CPURISCVState *env = &cpu->env;
> const char *warn_msg = "Profile %s mandates disabled extension %s";
> bool send_warn = profile->user_set && profile->enabled;
> - bool parent_enabled, profile_impl = true;
> + bool profile_impl = true;
> int i;
>
> #ifndef CONFIG_USER_ONLY
> @@ -773,12 +789,8 @@ static void riscv_cpu_validate_profile(RISCVCPU *cpu,
>
> profile->enabled = profile_impl;
>
> - if (profile->parent != NULL) {
> - parent_enabled = object_property_get_bool(OBJECT(cpu),
> - profile->parent->name,
> - NULL);
> - profile->enabled = profile->enabled && parent_enabled;
> - }
> + riscv_cpu_check_parent_profile(cpu, profile, profile->u_parent);
> + riscv_cpu_check_parent_profile(cpu, profile, profile->s_parent);
> }
>
> static void riscv_cpu_validate_profiles(RISCVCPU *cpu)
> @@ -1181,8 +1193,13 @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name,
> profile->user_set = true;
> profile->enabled = value;
>
> - if (profile->parent != NULL) {
> - object_property_set_bool(obj, profile->parent->name,
> + if (profile->u_parent != NULL) {
> + object_property_set_bool(obj, profile->u_parent->name,
> + profile->enabled, NULL);
> + }
> +
> + if (profile->s_parent != NULL) {
> + object_property_set_bool(obj, profile->s_parent->name,
> profile->enabled, NULL);
> }
>
> --
> 2.47.1
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v4 4/6] target/riscv: change priv_ver check in validate_profile()
2025-01-15 18:43 [PATCH v4 0/6] target/riscv: RVA23 profile support Daniel Henrique Barboza
` (2 preceding siblings ...)
2025-01-15 18:43 ` [PATCH v4 3/6] target/riscv: add profile u_parent and s_parent Daniel Henrique Barboza
@ 2025-01-15 18:43 ` Daniel Henrique Barboza
2025-01-31 0:07 ` Alistair Francis
2025-01-15 18:43 ` [PATCH v4 5/6] target/riscv: add RVA23U64 profile Daniel Henrique Barboza
` (2 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Daniel Henrique Barboza @ 2025-01-15 18:43 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, ajones, Daniel Henrique Barboza
The S profiles do a priv_ver check during validation to see if the
running priv_ver is compatible with it. This check is done by comparing
if the running priv_ver is equal to the priv_ver the profile specifies.
There is an universe where we added RVA23S64 support based on both
RVA23U64 and RVA22S64 and this error is being thrown:
qemu-system-riscv64: warning: Profile rva22s64 requires
priv spec v1.12.0, but priv ver v1.13.0 was set
We're enabling RVA22S64 (priv_ver 1.12) as a dependency of RVA23S64
(priv_ver 1.13) and complaining to users about what we did ourselves.
There's no drawback in allowing a profile to run in an env that has a
priv_ver newer than it's required by it. So, like Hiro Nakamura saves
the future by changing the past, change the priv_ver check now to allow
profiles to run in a newer priv_ver. This universe will have one less
warning to deal with.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
target/riscv/tcg/tcg-cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index c060b65fbc..de2a8c3f35 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -746,7 +746,7 @@ static void riscv_cpu_validate_profile(RISCVCPU *cpu,
#endif
if (profile->priv_spec != RISCV_PROFILE_ATTR_UNUSED &&
- profile->priv_spec != env->priv_ver) {
+ profile->priv_spec > env->priv_ver) {
profile_impl = false;
if (send_warn) {
--
2.47.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v4 4/6] target/riscv: change priv_ver check in validate_profile()
2025-01-15 18:43 ` [PATCH v4 4/6] target/riscv: change priv_ver check in validate_profile() Daniel Henrique Barboza
@ 2025-01-31 0:07 ` Alistair Francis
0 siblings, 0 replies; 14+ messages in thread
From: Alistair Francis @ 2025-01-31 0:07 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liwei1518,
zhiwei_liu, palmer, ajones
On Thu, Jan 16, 2025 at 4:45 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> The S profiles do a priv_ver check during validation to see if the
> running priv_ver is compatible with it. This check is done by comparing
> if the running priv_ver is equal to the priv_ver the profile specifies.
>
> There is an universe where we added RVA23S64 support based on both
> RVA23U64 and RVA22S64 and this error is being thrown:
>
> qemu-system-riscv64: warning: Profile rva22s64 requires
> priv spec v1.12.0, but priv ver v1.13.0 was set
>
> We're enabling RVA22S64 (priv_ver 1.12) as a dependency of RVA23S64
> (priv_ver 1.13) and complaining to users about what we did ourselves.
>
> There's no drawback in allowing a profile to run in an env that has a
> priv_ver newer than it's required by it. So, like Hiro Nakamura saves
> the future by changing the past, change the priv_ver check now to allow
> profiles to run in a newer priv_ver. This universe will have one less
> warning to deal with.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/tcg/tcg-cpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index c060b65fbc..de2a8c3f35 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -746,7 +746,7 @@ static void riscv_cpu_validate_profile(RISCVCPU *cpu,
> #endif
>
> if (profile->priv_spec != RISCV_PROFILE_ATTR_UNUSED &&
> - profile->priv_spec != env->priv_ver) {
> + profile->priv_spec > env->priv_ver) {
> profile_impl = false;
>
> if (send_warn) {
> --
> 2.47.1
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v4 5/6] target/riscv: add RVA23U64 profile
2025-01-15 18:43 [PATCH v4 0/6] target/riscv: RVA23 profile support Daniel Henrique Barboza
` (3 preceding siblings ...)
2025-01-15 18:43 ` [PATCH v4 4/6] target/riscv: change priv_ver check in validate_profile() Daniel Henrique Barboza
@ 2025-01-15 18:43 ` Daniel Henrique Barboza
2025-01-31 0:09 ` Alistair Francis
2025-01-15 18:43 ` [PATCH v4 6/6] target/riscv: add RVA23S64 profile Daniel Henrique Barboza
2025-01-31 0:25 ` [PATCH v4 0/6] target/riscv: RVA23 profile support Alistair Francis
6 siblings, 1 reply; 14+ messages in thread
From: Daniel Henrique Barboza @ 2025-01-15 18:43 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, ajones, Daniel Henrique Barboza
Add RVA23U64 as described in [1]. Add it as a child of RVA22U64 since
all RVA22U64 mandatory extensions are also present in RVA23U64. What's
left then is to list the mandatory extensions that are RVA23 only.
A new "rva23u64" CPU is also added.
[1] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 33 +++++++++++++++++++++++++++++++++
2 files changed, 34 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index d56b067bf2..53ead481a9 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -40,6 +40,7 @@
#define TYPE_RISCV_CPU_RV64E RISCV_CPU_TYPE_NAME("rv64e")
#define TYPE_RISCV_CPU_RVA22U64 RISCV_CPU_TYPE_NAME("rva22u64")
#define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64")
+#define TYPE_RISCV_CPU_RVA23U64 RISCV_CPU_TYPE_NAME("rva23u64")
#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e215b1004d..761da41e53 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2397,9 +2397,34 @@ static RISCVCPUProfile RVA22S64 = {
}
};
+/*
+ * All mandatory extensions from RVA22U64 are present
+ * in RVA23U64 so set RVA22 as a parent. We need to
+ * declare just the newly added mandatory extensions.
+ */
+static RISCVCPUProfile RVA23U64 = {
+ .u_parent = &RVA22U64,
+ .s_parent = NULL,
+ .name = "rva23u64",
+ .misa_ext = RVV,
+ .priv_spec = RISCV_PROFILE_ATTR_UNUSED,
+ .satp_mode = RISCV_PROFILE_ATTR_UNUSED,
+ .ext_offsets = {
+ CPU_CFG_OFFSET(ext_zvfhmin), CPU_CFG_OFFSET(ext_zvbb),
+ CPU_CFG_OFFSET(ext_zvkt), CPU_CFG_OFFSET(ext_zihintntl),
+ CPU_CFG_OFFSET(ext_zicond), CPU_CFG_OFFSET(ext_zimop),
+ CPU_CFG_OFFSET(ext_zcmop), CPU_CFG_OFFSET(ext_zcb),
+ CPU_CFG_OFFSET(ext_zfa), CPU_CFG_OFFSET(ext_zawrs),
+ CPU_CFG_OFFSET(ext_supm),
+
+ RISCV_PROFILE_EXT_LIST_END
+ }
+};
+
RISCVCPUProfile *riscv_profiles[] = {
&RVA22U64,
&RVA22S64,
+ &RVA23U64,
NULL,
};
@@ -2886,6 +2911,13 @@ static void rva22s64_profile_cpu_init(Object *obj)
RVA22S64.enabled = true;
}
+
+static void rva23u64_profile_cpu_init(Object *obj)
+{
+ rv64i_bare_cpu_init(obj);
+
+ RVA23U64.enabled = true;
+}
#endif
static const gchar *riscv_gdb_arch_name(CPUState *cs)
@@ -3165,6 +3197,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, MXL_RV64, rv64e_bare_cpu_init),
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, rva22u64_profile_cpu_init),
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, MXL_RV64, rva22s64_profile_cpu_init),
+ DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA23U64, MXL_RV64, rva23u64_profile_cpu_init),
#endif /* TARGET_RISCV64 */
};
--
2.47.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v4 5/6] target/riscv: add RVA23U64 profile
2025-01-15 18:43 ` [PATCH v4 5/6] target/riscv: add RVA23U64 profile Daniel Henrique Barboza
@ 2025-01-31 0:09 ` Alistair Francis
0 siblings, 0 replies; 14+ messages in thread
From: Alistair Francis @ 2025-01-31 0:09 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liwei1518,
zhiwei_liu, palmer, ajones
On Thu, Jan 16, 2025 at 4:45 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Add RVA23U64 as described in [1]. Add it as a child of RVA22U64 since
> all RVA22U64 mandatory extensions are also present in RVA23U64. What's
> left then is to list the mandatory extensions that are RVA23 only.
>
> A new "rva23u64" CPU is also added.
>
> [1] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu-qom.h | 1 +
> target/riscv/cpu.c | 33 +++++++++++++++++++++++++++++++++
> 2 files changed, 34 insertions(+)
>
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> index d56b067bf2..53ead481a9 100644
> --- a/target/riscv/cpu-qom.h
> +++ b/target/riscv/cpu-qom.h
> @@ -40,6 +40,7 @@
> #define TYPE_RISCV_CPU_RV64E RISCV_CPU_TYPE_NAME("rv64e")
> #define TYPE_RISCV_CPU_RVA22U64 RISCV_CPU_TYPE_NAME("rva22u64")
> #define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64")
> +#define TYPE_RISCV_CPU_RVA23U64 RISCV_CPU_TYPE_NAME("rva23u64")
> #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
> #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
> #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index e215b1004d..761da41e53 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2397,9 +2397,34 @@ static RISCVCPUProfile RVA22S64 = {
> }
> };
>
> +/*
> + * All mandatory extensions from RVA22U64 are present
> + * in RVA23U64 so set RVA22 as a parent. We need to
> + * declare just the newly added mandatory extensions.
> + */
> +static RISCVCPUProfile RVA23U64 = {
> + .u_parent = &RVA22U64,
> + .s_parent = NULL,
> + .name = "rva23u64",
> + .misa_ext = RVV,
> + .priv_spec = RISCV_PROFILE_ATTR_UNUSED,
> + .satp_mode = RISCV_PROFILE_ATTR_UNUSED,
> + .ext_offsets = {
> + CPU_CFG_OFFSET(ext_zvfhmin), CPU_CFG_OFFSET(ext_zvbb),
> + CPU_CFG_OFFSET(ext_zvkt), CPU_CFG_OFFSET(ext_zihintntl),
> + CPU_CFG_OFFSET(ext_zicond), CPU_CFG_OFFSET(ext_zimop),
> + CPU_CFG_OFFSET(ext_zcmop), CPU_CFG_OFFSET(ext_zcb),
> + CPU_CFG_OFFSET(ext_zfa), CPU_CFG_OFFSET(ext_zawrs),
> + CPU_CFG_OFFSET(ext_supm),
> +
> + RISCV_PROFILE_EXT_LIST_END
> + }
> +};
> +
> RISCVCPUProfile *riscv_profiles[] = {
> &RVA22U64,
> &RVA22S64,
> + &RVA23U64,
> NULL,
> };
>
> @@ -2886,6 +2911,13 @@ static void rva22s64_profile_cpu_init(Object *obj)
>
> RVA22S64.enabled = true;
> }
> +
> +static void rva23u64_profile_cpu_init(Object *obj)
> +{
> + rv64i_bare_cpu_init(obj);
> +
> + RVA23U64.enabled = true;
> +}
> #endif
>
> static const gchar *riscv_gdb_arch_name(CPUState *cs)
> @@ -3165,6 +3197,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E, MXL_RV64, rv64e_bare_cpu_init),
> DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, rva22u64_profile_cpu_init),
> DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, MXL_RV64, rva22s64_profile_cpu_init),
> + DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA23U64, MXL_RV64, rva23u64_profile_cpu_init),
> #endif /* TARGET_RISCV64 */
> };
>
> --
> 2.47.1
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v4 6/6] target/riscv: add RVA23S64 profile
2025-01-15 18:43 [PATCH v4 0/6] target/riscv: RVA23 profile support Daniel Henrique Barboza
` (4 preceding siblings ...)
2025-01-15 18:43 ` [PATCH v4 5/6] target/riscv: add RVA23U64 profile Daniel Henrique Barboza
@ 2025-01-15 18:43 ` Daniel Henrique Barboza
2025-01-31 0:13 ` Alistair Francis
2025-01-31 0:25 ` [PATCH v4 0/6] target/riscv: RVA23 profile support Alistair Francis
6 siblings, 1 reply; 14+ messages in thread
From: Daniel Henrique Barboza @ 2025-01-15 18:43 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, ajones, Daniel Henrique Barboza
Add RVA23S64 as described in [1]. This profile inherits all mandatory
extensions of RVA23U64 and RVA22S64, making it a child of both profiles.
A new "rva23s64" profile CPU is also added. This is the generated
riscv,isa for it (taken via -M dumpdtb):
rv64imafdcbvh_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_
ziccrse_zicond_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_
zmmul_za64rs_zaamo_zalrsc_zawrs_zfa_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbs_
zkt_zvbb_zve32f_zve32x_zve64f_zve64d_zve64x_zvfhmin_zvkb_zvkt_shcounterenw_
sha_shgatpa_shtvala_shvsatpa_shvstvala_shvstvecd_smnpm_smstateen_ssccptr_
sscofpmf_sscounterenw_ssnpm_ssstateen_sstc_sstvala_sstvecd_ssu64xl_
supm_svade_svinval_svnapot_svpbmt
[1] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 39 +++++++++++++++++++++++++++++++++++++++
2 files changed, 40 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 53ead481a9..4cfdb74891 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -41,6 +41,7 @@
#define TYPE_RISCV_CPU_RVA22U64 RISCV_CPU_TYPE_NAME("rva22u64")
#define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64")
#define TYPE_RISCV_CPU_RVA23U64 RISCV_CPU_TYPE_NAME("rva23u64")
+#define TYPE_RISCV_CPU_RVA23S64 RISCV_CPU_TYPE_NAME("rva23s64")
#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 761da41e53..adfce231a7 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2421,10 +2421,41 @@ static RISCVCPUProfile RVA23U64 = {
}
};
+/*
+ * As with RVA23U64, RVA23S64 also defines 'named features'.
+ *
+ * Cache related features that we consider enabled since we don't
+ * implement cache: Ssccptr
+ *
+ * Other named features that we already implement: Sstvecd, Sstvala,
+ * Sscounterenw, Ssu64xl
+ *
+ * The remaining features/extensions comes from RVA23S64.
+ */
+static RISCVCPUProfile RVA23S64 = {
+ .u_parent = &RVA23U64,
+ .s_parent = &RVA22S64,
+ .name = "rva23s64",
+ .misa_ext = RVS,
+ .priv_spec = PRIV_VERSION_1_13_0,
+ .satp_mode = VM_1_10_SV39,
+ .ext_offsets = {
+ /* New in RVA23S64 */
+ CPU_CFG_OFFSET(ext_svnapot), CPU_CFG_OFFSET(ext_sstc),
+ CPU_CFG_OFFSET(ext_sscofpmf), CPU_CFG_OFFSET(ext_ssnpm),
+
+ /* Named features: Sha */
+ CPU_CFG_OFFSET(ext_sha),
+
+ RISCV_PROFILE_EXT_LIST_END
+ }
+};
+
RISCVCPUProfile *riscv_profiles[] = {
&RVA22U64,
&RVA22S64,
&RVA23U64,
+ &RVA23S64,
NULL,
};
@@ -2918,6 +2949,13 @@ static void rva23u64_profile_cpu_init(Object *obj)
RVA23U64.enabled = true;
}
+
+static void rva23s64_profile_cpu_init(Object *obj)
+{
+ rv64i_bare_cpu_init(obj);
+
+ RVA23S64.enabled = true;
+}
#endif
static const gchar *riscv_gdb_arch_name(CPUState *cs)
@@ -3198,6 +3236,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, rva22u64_profile_cpu_init),
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, MXL_RV64, rva22s64_profile_cpu_init),
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA23U64, MXL_RV64, rva23u64_profile_cpu_init),
+ DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA23S64, MXL_RV64, rva23s64_profile_cpu_init),
#endif /* TARGET_RISCV64 */
};
--
2.47.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v4 6/6] target/riscv: add RVA23S64 profile
2025-01-15 18:43 ` [PATCH v4 6/6] target/riscv: add RVA23S64 profile Daniel Henrique Barboza
@ 2025-01-31 0:13 ` Alistair Francis
0 siblings, 0 replies; 14+ messages in thread
From: Alistair Francis @ 2025-01-31 0:13 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liwei1518,
zhiwei_liu, palmer, ajones
On Thu, Jan 16, 2025 at 4:45 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Add RVA23S64 as described in [1]. This profile inherits all mandatory
> extensions of RVA23U64 and RVA22S64, making it a child of both profiles.
>
> A new "rva23s64" profile CPU is also added. This is the generated
> riscv,isa for it (taken via -M dumpdtb):
>
> rv64imafdcbvh_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_
> ziccrse_zicond_zicntr_zicsr_zifencei_zihintntl_zihintpause_zihpm_zimop_
> zmmul_za64rs_zaamo_zalrsc_zawrs_zfa_zfhmin_zca_zcb_zcd_zcmop_zba_zbb_zbs_
> zkt_zvbb_zve32f_zve32x_zve64f_zve64d_zve64x_zvfhmin_zvkb_zvkt_shcounterenw_
> sha_shgatpa_shtvala_shvsatpa_shvstvala_shvstvecd_smnpm_smstateen_ssccptr_
> sscofpmf_sscounterenw_ssnpm_ssstateen_sstc_sstvala_sstvecd_ssu64xl_
> supm_svade_svinval_svnapot_svpbmt
>
> [1] https://github.com/riscv/riscv-profiles/blob/main/src/rva23-profile.adoc
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu-qom.h | 1 +
> target/riscv/cpu.c | 39 +++++++++++++++++++++++++++++++++++++++
> 2 files changed, 40 insertions(+)
>
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> index 53ead481a9..4cfdb74891 100644
> --- a/target/riscv/cpu-qom.h
> +++ b/target/riscv/cpu-qom.h
> @@ -41,6 +41,7 @@
> #define TYPE_RISCV_CPU_RVA22U64 RISCV_CPU_TYPE_NAME("rva22u64")
> #define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64")
> #define TYPE_RISCV_CPU_RVA23U64 RISCV_CPU_TYPE_NAME("rva23u64")
> +#define TYPE_RISCV_CPU_RVA23S64 RISCV_CPU_TYPE_NAME("rva23s64")
> #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
> #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
> #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 761da41e53..adfce231a7 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2421,10 +2421,41 @@ static RISCVCPUProfile RVA23U64 = {
> }
> };
>
> +/*
> + * As with RVA23U64, RVA23S64 also defines 'named features'.
> + *
> + * Cache related features that we consider enabled since we don't
> + * implement cache: Ssccptr
> + *
> + * Other named features that we already implement: Sstvecd, Sstvala,
> + * Sscounterenw, Ssu64xl
> + *
> + * The remaining features/extensions comes from RVA23S64.
> + */
> +static RISCVCPUProfile RVA23S64 = {
> + .u_parent = &RVA23U64,
> + .s_parent = &RVA22S64,
> + .name = "rva23s64",
> + .misa_ext = RVS,
> + .priv_spec = PRIV_VERSION_1_13_0,
> + .satp_mode = VM_1_10_SV39,
> + .ext_offsets = {
> + /* New in RVA23S64 */
> + CPU_CFG_OFFSET(ext_svnapot), CPU_CFG_OFFSET(ext_sstc),
> + CPU_CFG_OFFSET(ext_sscofpmf), CPU_CFG_OFFSET(ext_ssnpm),
> +
> + /* Named features: Sha */
> + CPU_CFG_OFFSET(ext_sha),
> +
> + RISCV_PROFILE_EXT_LIST_END
> + }
> +};
> +
> RISCVCPUProfile *riscv_profiles[] = {
> &RVA22U64,
> &RVA22S64,
> &RVA23U64,
> + &RVA23S64,
> NULL,
> };
>
> @@ -2918,6 +2949,13 @@ static void rva23u64_profile_cpu_init(Object *obj)
>
> RVA23U64.enabled = true;
> }
> +
> +static void rva23s64_profile_cpu_init(Object *obj)
> +{
> + rv64i_bare_cpu_init(obj);
> +
> + RVA23S64.enabled = true;
> +}
> #endif
>
> static const gchar *riscv_gdb_arch_name(CPUState *cs)
> @@ -3198,6 +3236,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, rva22u64_profile_cpu_init),
> DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, MXL_RV64, rva22s64_profile_cpu_init),
> DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA23U64, MXL_RV64, rva23u64_profile_cpu_init),
> + DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA23S64, MXL_RV64, rva23s64_profile_cpu_init),
> #endif /* TARGET_RISCV64 */
> };
>
> --
> 2.47.1
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v4 0/6] target/riscv: RVA23 profile support
2025-01-15 18:43 [PATCH v4 0/6] target/riscv: RVA23 profile support Daniel Henrique Barboza
` (5 preceding siblings ...)
2025-01-15 18:43 ` [PATCH v4 6/6] target/riscv: add RVA23S64 profile Daniel Henrique Barboza
@ 2025-01-31 0:25 ` Alistair Francis
6 siblings, 0 replies; 14+ messages in thread
From: Alistair Francis @ 2025-01-31 0:25 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, qemu-riscv, alistair.francis, bmeng, liwei1518,
zhiwei_liu, palmer, ajones
On Thu, Jan 16, 2025 at 4:44 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Hi,
>
> This new version has tweaks suggested by Drew in v3. No major changes
> were made.
>
> Patches based on alistair/riscv-to-apply.next.
>
> All patches acked.
>
> Changes from v3:
> - patch 3:
> - fix commit msg
> - drop the 'profile->enabled &&' check from riscv_cpu_check_parent_profile()
> - patch 6:
> - fix RVA23U64 -> RVA23S64 comment in the profile description
> - v3 link: https://lore.kernel.org/qemu-riscv/20250115134957.2179085-1-dbarboza@ventanamicro.com/
>
> Daniel Henrique Barboza (6):
> target/riscv: add ssu64xl
> target/riscv: use RVB in RVA22U64
> target/riscv: add profile u_parent and s_parent
> target/riscv: change priv_ver check in validate_profile()
> target/riscv: add RVA23U64 profile
> target/riscv: add RVA23S64 profile
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> target/riscv/cpu-qom.h | 2 +
> target/riscv/cpu.c | 81 ++++++++++++++++++++++++++++--
> target/riscv/cpu.h | 3 +-
> target/riscv/tcg/tcg-cpu.c | 37 ++++++++++----
> tests/data/acpi/riscv64/virt/RHCT | Bin 390 -> 400 bytes
> 5 files changed, 109 insertions(+), 14 deletions(-)
>
> --
> 2.47.1
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread