From: Alistair Francis <alistair23@gmail.com>
To: Ivan Klokov <ivan.klokov@syntacore.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
richard.henderson@linaro.org, pbonzini@redhat.com,
eduardo@habkost.net, marcel.apfelbaum@gmail.com,
philmd@linaro.org, wangyanan55@huawei.com, palmer@dabbelt.com,
alistair.francis@wdc.com, bin.meng@windriver.com,
liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com
Subject: Re: [PATCH v3 0/2] Support for print to log vector extension registers
Date: Fri, 2 Jun 2023 13:40:37 +1000 [thread overview]
Message-ID: <CAKmqyKNcmf=EaZ_kG1THoRV0turN09cUfKHXWUNCf6bKxNGsSw@mail.gmail.com> (raw)
In-Reply-To: <20230410124451.15929-1-ivan.klokov@syntacore.com>
On Mon, Apr 10, 2023 at 10:46 PM Ivan Klokov <ivan.klokov@syntacore.com> wrote:
>
> The patch added an ability to include VPU registers in the 'cpu' logging.
> ---
> v3:
> - split of the patch into two parts: general and RISC-V specific
> ---
>
> Ivan Klokov (2):
> util/log: Add vector registers to log
> target/riscv: Add RVV registers to log
I'm going to go ahead and merge this
Applied to riscv-to-apply.next
Alistair
>
> accel/tcg/cpu-exec.c | 3 +++
> include/hw/core/cpu.h | 2 ++
> include/qemu/log.h | 1 +
> target/riscv/cpu.c | 56 ++++++++++++++++++++++++++++++++++++++++++-
> util/log.c | 2 ++
> 5 files changed, 63 insertions(+), 1 deletion(-)
>
> --
> 2.34.1
>
>
prev parent reply other threads:[~2023-06-02 3:41 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-10 12:44 [PATCH v3 0/2] Support for print to log vector extension registers Ivan Klokov
2023-04-10 12:44 ` [PATCH v3 1/2] util/log: Add vector registers to log Ivan Klokov
2023-04-12 10:56 ` Alistair Francis
2023-04-10 12:44 ` [PATCH v3 2/2] target/riscv: Add RVV " Ivan Klokov
2023-04-12 10:57 ` Alistair Francis
2023-06-02 3:43 ` Alistair Francis
2023-06-02 10:20 ` Philippe Mathieu-Daudé
2023-06-02 3:40 ` Alistair Francis [this message]
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