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To: Jim Shu Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::a34; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa34.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Nov 7, 2024 at 4:32=E2=80=AFPM Jim Shu wrote: > > Larger initrd image will overlap the DTB at 3GB address. Since 64-bit > system doesn't have 32-bit addressable issue, we just load DTB to the end > of dram in 64-bit system. > > Signed-off-by: Jim Shu > --- > hw/riscv/boot.c | 8 ++++++-- > hw/riscv/microchip_pfsoc.c | 4 ++-- > hw/riscv/sifive_u.c | 4 ++-- > hw/riscv/spike.c | 4 ++-- > hw/riscv/virt.c | 2 +- > include/hw/riscv/boot.h | 2 +- > 6 files changed, 14 insertions(+), 10 deletions(-) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index 2e319168db..4e4e106a2b 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -293,7 +293,7 @@ out: > * The FDT is fdt_packed() during the calculation. > */ > uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, > - MachineState *ms) > + MachineState *ms, RISCVHartArrayState *h= arts) > { > int ret =3D fdt_pack(ms->fdt); > hwaddr dram_end, temp; > @@ -321,7 +321,11 @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hw= addr dram_size, > * Thus, put it at an 2MB aligned address that less than fdt size fr= om the > * end of dram or 3GB whichever is lesser. > */ We should probably update this comment to describe what happens for 64-bit systems. Otherwise: Reviewed-by: Alistair Francis Alistair > - temp =3D (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram= _end; > + if (!riscv_is_32bit(harts)) { > + temp =3D dram_end; > + } else { > + temp =3D (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : = dram_end; > + } > > return QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); > } > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > index f9a3b43d2e..ba8b0a2c26 100644 > --- a/hw/riscv/microchip_pfsoc.c > +++ b/hw/riscv/microchip_pfsoc.c > @@ -519,7 +519,7 @@ static void microchip_icicle_kit_machine_init(Machine= State *machine) > bool kernel_as_payload =3D false; > target_ulong firmware_end_addr, kernel_start_addr; > uint64_t kernel_entry; > - uint32_t fdt_load_addr; > + uint64_t fdt_load_addr; > DriveInfo *dinfo =3D drive_get(IF_SD, 0, 0); > > /* Sanity check on RAM size */ > @@ -625,7 +625,7 @@ static void microchip_icicle_kit_machine_init(Machine= State *machine) > /* Compute the fdt load address in dram */ > fdt_load_addr =3D riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_= DRAM_LO].base, > memmap[MICROCHIP_PFSOC_DR= AM_LO].size, > - machine); > + machine, &s->soc.u_cpus); > riscv_load_fdt(fdt_load_addr, machine->fdt); > > /* Load the reset vector */ > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index c5e74126b1..05467e833a 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -519,7 +519,7 @@ static void sifive_u_machine_init(MachineState *machi= ne) > const char *firmware_name; > uint32_t start_addr_hi32 =3D 0x00000000; > int i; > - uint32_t fdt_load_addr; > + uint64_t fdt_load_addr; > uint64_t kernel_entry; > DriveInfo *dinfo; > BlockBackend *blk; > @@ -606,7 +606,7 @@ static void sifive_u_machine_init(MachineState *machi= ne) > > fdt_load_addr =3D riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].b= ase, > memmap[SIFIVE_U_DEV_DRAM].siz= e, > - machine); > + machine, &s->soc.u_cpus); > riscv_load_fdt(fdt_load_addr, machine->fdt); > > if (!riscv_is_32bit(&s->soc.u_cpus)) { > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index fceb91d946..acd7ab1ae1 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -201,7 +201,7 @@ static void spike_board_init(MachineState *machine) > hwaddr firmware_load_addr =3D memmap[SPIKE_DRAM].base; > target_ulong kernel_start_addr; > char *firmware_name; > - uint32_t fdt_load_addr; > + uint64_t fdt_load_addr; > uint64_t kernel_entry; > char *soc_name; > int i, base_hartid, hart_count; > @@ -317,7 +317,7 @@ static void spike_board_init(MachineState *machine) > > fdt_load_addr =3D riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base, > memmap[SPIKE_DRAM].size, > - machine); > + machine, &s->soc[0]); > riscv_load_fdt(fdt_load_addr, machine->fdt); > > /* load the reset vector */ > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index 45a8c4f819..761bce3304 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -1424,7 +1424,7 @@ static void virt_machine_done(Notifier *notifier, v= oid *data) > > fdt_load_addr =3D riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, > memmap[VIRT_DRAM].size, > - machine); > + machine, &s->soc[0]); > riscv_load_fdt(fdt_load_addr, machine->fdt); > > /* load the reset vector */ > diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h > index f778b560de..34a80c5ff4 100644 > --- a/include/hw/riscv/boot.h > +++ b/include/hw/riscv/boot.h > @@ -49,7 +49,7 @@ target_ulong riscv_load_kernel(MachineState *machine, > bool load_initrd, > symbol_fn_t sym_cb); > uint64_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size, > - MachineState *ms); > + MachineState *ms, RISCVHartArrayState *h= arts); > void riscv_load_fdt(hwaddr fdt_addr, void *fdt); > void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayStat= e *harts, > hwaddr saddr, > -- > 2.17.1 > >