Re: [PATCH 0/5] Improve Microchip Polarfire SoC customization

[Alistair Francis <alistair23@gmail.com>]

On Fri, Feb 21, 2025 at 4:31 AM Conor Dooley <conor@kernel.org> wrote:
>
> +cc qemu-riscv, Alistar.
>
> On Fri, Feb 14, 2025 at 07:24:37AM +0100, Sebastian Huber wrote:
> > Booting the microchip-icicle-kit machine using the latest PolarFire SoC
> > Hart Software Services (HSS) no longer works since Qemu lacks support
> > for several registers (clocks, DRAM controller). Also reading from the
> > SDCard does not work currently.
>
> On that note, I think the inaccurate docs about polarfire should be
> removed. There's a wiki page here with dead links, or links to things
> that do not work anymore:
> https://wiki.qemu.org/Documentation/Platforms/RISCV#Microchip_PolarFire_SoC_Icicle_Kit
> I think the whole section should be removed, find it kinda odd that
> there's a polarfire section but not for any other board. Either way,
> it's talking about something that just does not work, the current HSS
> and Yocto don't boot.

The wiki is independent of the QEMU code base, so you can modify it. I
agree that we should remove outdated/wrong information as it's very
confusing to users.

>
> There's also a docs page here:
> https://www.qemu.org/docs/master/system/riscv/microchip-icicle-kit.html

That is generated from the QEMU codebase
`docs/system/riscv/microchip-icicle-kit.rst` and should be updated,
ideally with this patch set

> that has a copy of the table your patch 4 modifies, that probably should
> be updated to match your changes.
>
> In a similar vein to the wiki, it talks about the HSS and booting a
> yocto wic image. I think those should be deleted since they don't work.

Agreed

Alistair

>
> Alistar/Other RISC-V folks, what do you think? Bin wrote the port but
> seems to be AFK and I don't have the capacity to fix any of that stuff
> on top of what I already do in my spare time - do you agree that
> deleting the now inaccurate docs makes sense?
>
> > In order to allow tests runs for real-time kernels such as RTEMS and
> > Zephyr, improve the boot customization. This patch set enables a direct
> > run of kernel executables, for example:
> >
> > qemu-system-riscv64 -no-reboot -nographic \
> >   -serial null -serial mon:stdio \
> >   -smp 2 \
> >   -bios none \
> >   -machine microchip-icicle-kit,clint-timebase-frequency=10000000 \
> >   -kernel rtos.elf
>
> The series breaks my usage:
> qemu//build/qemu-system-riscv64 -M microchip-icicle-kit \
>         -m 3G -smp 5 \
>         -kernel vmlinux.bin \
>         -dtb riscvpc.dtb \
>         -initrd initramfs.cpio.gz \
>         -display none -serial null \
>         -serial mon:stdio \
>         -D qemu.log -d unimp
> opensbi-riscv64-generic-fw_dynamic.bin: No such file or directory
> qemu-system-riscv64: could not load firmware 'opensbi-riscv64-generic-fw_dynamic.bin'
> make: *** [Makefile:305: qemu-icicle] Error 1
>
> Figure it is likely to be your patch 4? The file does exist, so probably
> some sort of path-to-it issues?
>
> Cheers,
> Conor.
>
> >
> > Sebastian Huber (5):
> >   hw/misc: Add MPFS system reset support
> >   hw/riscv: More flexible FDT placement for MPFS
> >   hw/riscv: Make FDT optional for MPFS
> >   hw/riscv: Allow direct start of kernel for MPFS
> >   hw/riscv: Configurable MPFS CLINT timebase freq
> >
> >  hw/misc/mchp_pfsoc_sysreg.c        |   7 ++
> >  hw/riscv/microchip_pfsoc.c         | 147 +++++++++++++++++++++--------
> >  include/hw/riscv/microchip_pfsoc.h |   1 +
> >  3 files changed, 115 insertions(+), 40 deletions(-)
> >
> > --
> > 2.43.0
> >
> >