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Sun, 23 Feb 2025 21:14:27 -0800 (PST) MIME-Version: 1.0 References: <20250214062443.9936-1-sebastian.huber@embedded-brains.de> <20250220-reggae-hardness-907e385516d8@spud> In-Reply-To: <20250220-reggae-hardness-907e385516d8@spud> From: Alistair Francis Date: Mon, 24 Feb 2025 15:14:00 +1000 X-Gm-Features: AWEUYZlAb2LXUi9ehUHDn8C9xhjRaogHo7sWUQILq5TJI_nY77i8tsgSmjC4WHU Message-ID: Subject: Re: [PATCH 0/5] Improve Microchip Polarfire SoC customization To: Conor Dooley Cc: Sebastian Huber , qemu-devel@nongnu.org, Conor Dooley , Bin Meng , alistair.francis@wdc.com, qemu-riscv@nongnu.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::e2b; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe2b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Feb 21, 2025 at 4:31=E2=80=AFAM Conor Dooley wro= te: > > +cc qemu-riscv, Alistar. > > On Fri, Feb 14, 2025 at 07:24:37AM +0100, Sebastian Huber wrote: > > Booting the microchip-icicle-kit machine using the latest PolarFire SoC > > Hart Software Services (HSS) no longer works since Qemu lacks support > > for several registers (clocks, DRAM controller). Also reading from the > > SDCard does not work currently. > > On that note, I think the inaccurate docs about polarfire should be > removed. There's a wiki page here with dead links, or links to things > that do not work anymore: > https://wiki.qemu.org/Documentation/Platforms/RISCV#Microchip_PolarFire_S= oC_Icicle_Kit > I think the whole section should be removed, find it kinda odd that > there's a polarfire section but not for any other board. Either way, > it's talking about something that just does not work, the current HSS > and Yocto don't boot. The wiki is independent of the QEMU code base, so you can modify it. I agree that we should remove outdated/wrong information as it's very confusing to users. > > There's also a docs page here: > https://www.qemu.org/docs/master/system/riscv/microchip-icicle-kit.html That is generated from the QEMU codebase `docs/system/riscv/microchip-icicle-kit.rst` and should be updated, ideally with this patch set > that has a copy of the table your patch 4 modifies, that probably should > be updated to match your changes. > > In a similar vein to the wiki, it talks about the HSS and booting a > yocto wic image. I think those should be deleted since they don't work. Agreed Alistair > > Alistar/Other RISC-V folks, what do you think? Bin wrote the port but > seems to be AFK and I don't have the capacity to fix any of that stuff > on top of what I already do in my spare time - do you agree that > deleting the now inaccurate docs makes sense? > > > In order to allow tests runs for real-time kernels such as RTEMS and > > Zephyr, improve the boot customization. This patch set enables a direct > > run of kernel executables, for example: > > > > qemu-system-riscv64 -no-reboot -nographic \ > > -serial null -serial mon:stdio \ > > -smp 2 \ > > -bios none \ > > -machine microchip-icicle-kit,clint-timebase-frequency=3D10000000 \ > > -kernel rtos.elf > > The series breaks my usage: > qemu//build/qemu-system-riscv64 -M microchip-icicle-kit \ > -m 3G -smp 5 \ > -kernel vmlinux.bin \ > -dtb riscvpc.dtb \ > -initrd initramfs.cpio.gz \ > -display none -serial null \ > -serial mon:stdio \ > -D qemu.log -d unimp > opensbi-riscv64-generic-fw_dynamic.bin: No such file or directory > qemu-system-riscv64: could not load firmware 'opensbi-riscv64-generic-fw_= dynamic.bin' > make: *** [Makefile:305: qemu-icicle] Error 1 > > Figure it is likely to be your patch 4? The file does exist, so probably > some sort of path-to-it issues? > > Cheers, > Conor. > > > > > Sebastian Huber (5): > > hw/misc: Add MPFS system reset support > > hw/riscv: More flexible FDT placement for MPFS > > hw/riscv: Make FDT optional for MPFS > > hw/riscv: Allow direct start of kernel for MPFS > > hw/riscv: Configurable MPFS CLINT timebase freq > > > > hw/misc/mchp_pfsoc_sysreg.c | 7 ++ > > hw/riscv/microchip_pfsoc.c | 147 +++++++++++++++++++++-------- > > include/hw/riscv/microchip_pfsoc.h | 1 + > > 3 files changed, 115 insertions(+), 40 deletions(-) > > > > -- > > 2.43.0 > > > >