qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
* [PATCH V3 0/6] Support RISC-V migration
@ 2020-10-23  9:12 Yifei Jiang
  2020-10-23  9:12 ` [PATCH V3 1/6] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit Yifei Jiang
                   ` (5 more replies)
  0 siblings, 6 replies; 14+ messages in thread
From: Yifei Jiang @ 2020-10-23  9:12 UTC (permalink / raw)
  To: qemu-devel, qemu-riscv
  Cc: zhang.zhanghailiang, sagark, kbastian, victor.zhangxiaofeng,
	richard.henderson, Yifei Jiang, Alistair.Francis, yinyipeng1,
	palmer, wu.wubin, dengkai1

This patches supported RISC-V migration based on tcg accel. And we have
verified related migration features such as snapshot and live migration.

A few weeks ago, we submitted RFC patches about supporting RISC-V migration
based on kvm accel: https://www.spinics.net/lists/kvm/msg223605.html.
And we found that tcg accelerated migration can be supported with a few
changes. Most of the devices have already implemented the migration
interface, so, to achieve the tcg accelerated migration, we just need to
add vmstate of both cpu and sifive_plic.

Changes since v2:
1. Move vmstate_riscv_cpu declaration to internals.h.
2. Merge m/vsstatus and m/vsstatush into one uint64_t unit.

Changes since v1:
1. Add license head to target/riscv/machine.c.
2. Regenerate some state of PMP at post_load hook.

Yifei Jiang (6):
  target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit
  target/riscv: Add basic vmstate description of CPU
  target/riscv: Add PMP state description
  target/riscv: Add H extension state description
  target/riscv: Add V extension state description
  target/riscv: Add sifive_plic vmstate

 hw/intc/sifive_plic.c     |  26 ++++-
 hw/intc/sifive_plic.h     |   1 +
 target/riscv/cpu.c        |  16 ++--
 target/riscv/cpu.h        |  16 +---
 target/riscv/cpu_bits.h   |  16 ++--
 target/riscv/cpu_helper.c |  72 ++++++--------
 target/riscv/csr.c        |  28 +++---
 target/riscv/internals.h  |   4 +
 target/riscv/machine.c    | 196 ++++++++++++++++++++++++++++++++++++++
 target/riscv/meson.build  |   3 +-
 target/riscv/op_helper.c  |  49 +++++-----
 target/riscv/pmp.c        |  29 +++---
 target/riscv/pmp.h        |   2 +
 13 files changed, 331 insertions(+), 127 deletions(-)
 create mode 100644 target/riscv/machine.c

-- 
2.19.1



^ permalink raw reply	[flat|nested] 14+ messages in thread
end of thread, other threads:[~2020-10-24  0:15 UTC | newest]

Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-10-23  9:12 [PATCH V3 0/6] Support RISC-V migration Yifei Jiang
2020-10-23  9:12 ` [PATCH V3 1/6] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit Yifei Jiang
2020-10-23  9:41   ` Jiangyifei
2020-10-23 23:50   ` Alistair Francis
2020-10-23  9:12 ` [PATCH V3 2/6] target/riscv: Add basic vmstate description of CPU Yifei Jiang
2020-10-23 23:52   ` Alistair Francis
2020-10-23  9:12 ` [PATCH V3 3/6] target/riscv: Add PMP state description Yifei Jiang
2020-10-23 23:59   ` Alistair Francis
2020-10-23  9:12 ` [PATCH V3 4/6] target/riscv: Add H extension " Yifei Jiang
2020-10-24  0:00   ` Alistair Francis
2020-10-23  9:12 ` [PATCH V3 5/6] target/riscv: Add V " Yifei Jiang
2020-10-24  0:01   ` Alistair Francis
2020-10-23  9:12 ` [PATCH V3 6/6] target/riscv: Add sifive_plic vmstate Yifei Jiang
2020-10-24  0:02   ` Alistair Francis

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).