qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Alistair Francis <alistair23@gmail.com>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>
Cc: guoren@linux.alibaba.com,
	"open list:RISC-V" <qemu-riscv@nongnu.org>,
	Richard Henderson <richard.henderson@linaro.org>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	wxy194768@alibaba-inc.com,
	Chih-Min Chao <chihmin.chao@sifive.com>,
	wenmeng_zhang@c-sky.com, Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v7 30/61] target/riscv: vector single-width floating-point add/subtract instructions
Date: Fri, 17 Apr 2020 15:07:30 -0700	[thread overview]
Message-ID: <CAKmqyKNg9oGynDHAMcmOZ_RtNpRNnxJa1tOSRDWVA0zqkcxnoA@mail.gmail.com> (raw)
In-Reply-To: <20200330153633.15298-31-zhiwei_liu@c-sky.com>

On Mon, Mar 30, 2020 at 9:37 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/helper.h                   |  16 ++++
>  target/riscv/insn32.decode              |   5 +
>  target/riscv/insn_trans/trans_rvv.inc.c | 116 ++++++++++++++++++++++++
>  target/riscv/vector_helper.c            | 111 +++++++++++++++++++++++
>  4 files changed, 248 insertions(+)
>
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 7f7fdcb451..3031a941c2 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -797,3 +797,19 @@ DEF_HELPER_6(vnclipu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
>  DEF_HELPER_6(vnclip_vx_b, void, ptr, ptr, tl, ptr, env, i32)
>  DEF_HELPER_6(vnclip_vx_h, void, ptr, ptr, tl, ptr, env, i32)
>  DEF_HELPER_6(vnclip_vx_w, void, ptr, ptr, tl, ptr, env, i32)
> +
> +DEF_HELPER_6(vfadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vfadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vfadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vfsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vfsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vfsub_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vfadd_vf_h, void, ptr, ptr, i64, ptr, env, i32)
> +DEF_HELPER_6(vfadd_vf_w, void, ptr, ptr, i64, ptr, env, i32)
> +DEF_HELPER_6(vfadd_vf_d, void, ptr, ptr, i64, ptr, env, i32)
> +DEF_HELPER_6(vfsub_vf_h, void, ptr, ptr, i64, ptr, env, i32)
> +DEF_HELPER_6(vfsub_vf_w, void, ptr, ptr, i64, ptr, env, i32)
> +DEF_HELPER_6(vfsub_vf_d, void, ptr, ptr, i64, ptr, env, i32)
> +DEF_HELPER_6(vfrsub_vf_h, void, ptr, ptr, i64, ptr, env, i32)
> +DEF_HELPER_6(vfrsub_vf_w, void, ptr, ptr, i64, ptr, env, i32)
> +DEF_HELPER_6(vfrsub_vf_d, void, ptr, ptr, i64, ptr, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 8b898f9bad..c8e3f10162 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -443,6 +443,11 @@ vnclipu_vi      101110 . ..... ..... 011 ..... 1010111 @r_vm
>  vnclip_vv       101111 . ..... ..... 000 ..... 1010111 @r_vm
>  vnclip_vx       101111 . ..... ..... 100 ..... 1010111 @r_vm
>  vnclip_vi       101111 . ..... ..... 011 ..... 1010111 @r_vm
> +vfadd_vv        000000 . ..... ..... 001 ..... 1010111 @r_vm
> +vfadd_vf        000000 . ..... ..... 101 ..... 1010111 @r_vm
> +vfsub_vv        000010 . ..... ..... 001 ..... 1010111 @r_vm
> +vfsub_vf        000010 . ..... ..... 101 ..... 1010111 @r_vm
> +vfrsub_vf       100111 . ..... ..... 101 ..... 1010111 @r_vm
>
>  vsetvli         0 ........... ..... 111 ..... 1010111  @r2_zimm
>  vsetvl          1000000 ..... ..... 111 ..... 1010111  @r
> diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
> index d03ec2688f..9a8fb18adc 100644
> --- a/target/riscv/insn_trans/trans_rvv.inc.c
> +++ b/target/riscv/insn_trans/trans_rvv.inc.c
> @@ -1807,3 +1807,119 @@ GEN_OPIVX_NARROW_TRANS(vnclipu_vx)
>  GEN_OPIVX_NARROW_TRANS(vnclip_vx)
>  GEN_OPIVI_NARROW_TRANS(vnclipu_vi, 1, vnclipu_vx)
>  GEN_OPIVI_NARROW_TRANS(vnclip_vi, 1, vnclip_vx)
> +
> +/*
> + *** Vector Float Point Arithmetic Instructions
> + */
> +/* Vector Single-Width Floating-Point Add/Subtract Instructions */
> +
> +/*
> + * If the current SEW does not correspond to a supported IEEE floating-point
> + * type, an illegal instruction exception is raised.
> + */
> +static bool opfvv_check(DisasContext *s, arg_rmrr *a)
> +{
> +    return (vext_check_isa_ill(s) &&
> +            vext_check_overlap_mask(s, a->rd, a->vm, false) &&
> +            vext_check_reg(s, a->rd, false) &&
> +            vext_check_reg(s, a->rs2, false) &&
> +            vext_check_reg(s, a->rs1, false) &&
> +            (s->sew != 0));
> +}
> +
> +/* OPFVV without GVEC IR */
> +#define GEN_OPFVV_TRANS(NAME, CHECK)                               \
> +static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
> +{                                                                  \
> +    if (CHECK(s, a)) {                                             \
> +        uint32_t data = 0;                                         \
> +        static gen_helper_gvec_4_ptr * const fns[3] = {            \
> +            gen_helper_##NAME##_h,                                 \
> +            gen_helper_##NAME##_w,                                 \
> +            gen_helper_##NAME##_d,                                 \
> +        };                                                         \
> +        TCGLabel *over = gen_new_label();                          \
> +        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
> +                                                                   \
> +        data = FIELD_DP32(data, VDATA, MLEN, s->mlen);             \
> +        data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
> +        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
> +        tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
> +                           vreg_ofs(s, a->rs1),                    \
> +                           vreg_ofs(s, a->rs2), cpu_env, 0,        \
> +                           s->vlen / 8, data, fns[s->sew - 1]);    \
> +        gen_set_label(over);                                       \
> +        return true;                                               \
> +    }                                                              \
> +    return false;                                                  \
> +}
> +GEN_OPFVV_TRANS(vfadd_vv, opfvv_check)
> +GEN_OPFVV_TRANS(vfsub_vv, opfvv_check)
> +
> +typedef void gen_helper_opfvf(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_ptr,
> +                              TCGv_env, TCGv_i32);
> +
> +static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
> +                        uint32_t data, gen_helper_opfvf *fn, DisasContext *s)
> +{
> +    TCGv_ptr dest, src2, mask;
> +    TCGv_i32 desc;
> +
> +    TCGLabel *over = gen_new_label();
> +    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
> +
> +    dest = tcg_temp_new_ptr();
> +    mask = tcg_temp_new_ptr();
> +    src2 = tcg_temp_new_ptr();
> +    desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
> +
> +    tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
> +    tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
> +    tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
> +
> +    fn(dest, mask, cpu_fpr[rs1], src2, cpu_env, desc);
> +
> +    tcg_temp_free_ptr(dest);
> +    tcg_temp_free_ptr(mask);
> +    tcg_temp_free_ptr(src2);
> +    tcg_temp_free_i32(desc);
> +    gen_set_label(over);
> +    return true;
> +}
> +
> +static bool opfvf_check(DisasContext *s, arg_rmrr *a)
> +{
> +/*
> + * If the current SEW does not correspond to a supported IEEE floating-point
> + * type, an illegal instruction exception is raised
> + */
> +    return (vext_check_isa_ill(s) &&
> +            vext_check_overlap_mask(s, a->rd, a->vm, false) &&
> +            vext_check_reg(s, a->rd, false) &&
> +            vext_check_reg(s, a->rs2, false) &&
> +            (s->sew != 0));
> +}
> +
> +/* OPFVF without GVEC IR */
> +#define GEN_OPFVF_TRANS(NAME, CHECK)                              \
> +static bool trans_##NAME(DisasContext *s, arg_rmrr *a)            \
> +{                                                                 \
> +    if (CHECK(s, a)) {                                            \
> +        uint32_t data = 0;                                        \
> +        static gen_helper_opfvf *const fns[3] = {                 \
> +            gen_helper_##NAME##_h,                                \
> +            gen_helper_##NAME##_w,                                \
> +            gen_helper_##NAME##_d,                                \
> +        };                                                        \
> +        data = FIELD_DP32(data, VDATA, MLEN, s->mlen);            \
> +        data = FIELD_DP32(data, VDATA, VM, a->vm);                \
> +        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);            \
> +        return opfvf_trans(a->rd, a->rs1, a->rs2, data,           \
> +                           fns[s->sew - 1], s);                   \
> +    }                                                             \
> +    return false;                                                 \
> +}
> +
> +GEN_OPFVF_TRANS(vfadd_vf,  opfvf_check)
> +GEN_OPFVF_TRANS(vfsub_vf,  opfvf_check)
> +GEN_OPFVF_TRANS(vfrsub_vf,  opfvf_check)
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 502656d005..af343e9bf9 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -21,6 +21,7 @@
>  #include "exec/memop.h"
>  #include "exec/exec-all.h"
>  #include "exec/helper-proto.h"
> +#include "fpu/softfloat.h"
>  #include "tcg/tcg-gvec-desc.h"
>  #include "internals.h"
>  #include <math.h>
> @@ -3166,3 +3167,113 @@ RVVCALL(OPIVX2_RM, vnclipu_vx_w, NOP_UUU_W, H4, H8, vnclipu32)
>  GEN_VEXT_VX_RM(vnclipu_vx_b, 1, 1, clearb)
>  GEN_VEXT_VX_RM(vnclipu_vx_h, 2, 2, clearh)
>  GEN_VEXT_VX_RM(vnclipu_vx_w, 4, 4, clearl)
> +
> +/*
> + *** Vector Float Point Arithmetic Instructions
> + */
> +/* Vector Single-Width Floating-Point Add/Subtract Instructions */
> +#define OPFVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP)   \
> +static void do_##NAME(void *vd, void *vs1, void *vs2, int i,   \
> +                      CPURISCVState *env)                      \
> +{                                                              \
> +    TX1 s1 = *((T1 *)vs1 + HS1(i));                            \
> +    TX2 s2 = *((T2 *)vs2 + HS2(i));                            \
> +    *((TD *)vd + HD(i)) = OP(s2, s1, &env->fp_status);         \
> +}
> +
> +#define GEN_VEXT_VV_ENV(NAME, ESZ, DSZ, CLEAR_FN)         \
> +void HELPER(NAME)(void *vd, void *v0, void *vs1,          \
> +                  void *vs2, CPURISCVState *env,          \
> +                  uint32_t desc)                          \
> +{                                                         \
> +    uint32_t vlmax = vext_maxsz(desc) / ESZ;              \
> +    uint32_t mlen = vext_mlen(desc);                      \
> +    uint32_t vm = vext_vm(desc);                          \
> +    uint32_t vl = env->vl;                                \
> +    uint32_t i;                                           \
> +                                                          \
> +    for (i = 0; i < vl; i++) {                            \
> +        if (!vm && !vext_elem_mask(v0, mlen, i)) {        \
> +            continue;                                     \
> +        }                                                 \
> +        do_##NAME(vd, vs1, vs2, i, env);                  \
> +    }                                                     \
> +    CLEAR_FN(vd, vl, vl * DSZ,  vlmax * DSZ);             \
> +}
> +
> +RVVCALL(OPFVV2, vfadd_vv_h, OP_UUU_H, H2, H2, H2, float16_add)
> +RVVCALL(OPFVV2, vfadd_vv_w, OP_UUU_W, H4, H4, H4, float32_add)
> +RVVCALL(OPFVV2, vfadd_vv_d, OP_UUU_D, H8, H8, H8, float64_add)
> +GEN_VEXT_VV_ENV(vfadd_vv_h, 2, 2, clearh)
> +GEN_VEXT_VV_ENV(vfadd_vv_w, 4, 4, clearl)
> +GEN_VEXT_VV_ENV(vfadd_vv_d, 8, 8, clearq)
> +
> +#define OPFVF2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP)        \
> +static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \
> +                      CPURISCVState *env)                      \
> +{                                                              \
> +    TX2 s2 = *((T2 *)vs2 + HS2(i));                            \
> +    *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1, &env->fp_status);\
> +}
> +
> +#define GEN_VEXT_VF(NAME, ESZ, DSZ, CLEAR_FN)             \
> +void HELPER(NAME)(void *vd, void *v0, uint64_t s1,        \
> +                  void *vs2, CPURISCVState *env,          \
> +                  uint32_t desc)                          \
> +{                                                         \
> +    uint32_t vlmax = vext_maxsz(desc) / ESZ;              \
> +    uint32_t mlen = vext_mlen(desc);                      \
> +    uint32_t vm = vext_vm(desc);                          \
> +    uint32_t vl = env->vl;                                \
> +    uint32_t i;                                           \
> +                                                          \
> +    for (i = 0; i < vl; i++) {                            \
> +        if (!vm && !vext_elem_mask(v0, mlen, i)) {        \
> +            continue;                                     \
> +        }                                                 \
> +        do_##NAME(vd, s1, vs2, i, env);                   \
> +    }                                                     \
> +    CLEAR_FN(vd, vl, vl * DSZ,  vlmax * DSZ);             \
> +}
> +
> +RVVCALL(OPFVF2, vfadd_vf_h, OP_UUU_H, H2, H2, float16_add)
> +RVVCALL(OPFVF2, vfadd_vf_w, OP_UUU_W, H4, H4, float32_add)
> +RVVCALL(OPFVF2, vfadd_vf_d, OP_UUU_D, H8, H8, float64_add)
> +GEN_VEXT_VF(vfadd_vf_h, 2, 2, clearh)
> +GEN_VEXT_VF(vfadd_vf_w, 4, 4, clearl)
> +GEN_VEXT_VF(vfadd_vf_d, 8, 8, clearq)
> +
> +RVVCALL(OPFVV2, vfsub_vv_h, OP_UUU_H, H2, H2, H2, float16_sub)
> +RVVCALL(OPFVV2, vfsub_vv_w, OP_UUU_W, H4, H4, H4, float32_sub)
> +RVVCALL(OPFVV2, vfsub_vv_d, OP_UUU_D, H8, H8, H8, float64_sub)
> +GEN_VEXT_VV_ENV(vfsub_vv_h, 2, 2, clearh)
> +GEN_VEXT_VV_ENV(vfsub_vv_w, 4, 4, clearl)
> +GEN_VEXT_VV_ENV(vfsub_vv_d, 8, 8, clearq)
> +RVVCALL(OPFVF2, vfsub_vf_h, OP_UUU_H, H2, H2, float16_sub)
> +RVVCALL(OPFVF2, vfsub_vf_w, OP_UUU_W, H4, H4, float32_sub)
> +RVVCALL(OPFVF2, vfsub_vf_d, OP_UUU_D, H8, H8, float64_sub)
> +GEN_VEXT_VF(vfsub_vf_h, 2, 2, clearh)
> +GEN_VEXT_VF(vfsub_vf_w, 4, 4, clearl)
> +GEN_VEXT_VF(vfsub_vf_d, 8, 8, clearq)
> +
> +static uint16_t float16_rsub(uint16_t a, uint16_t b, float_status *s)
> +{
> +    return float16_sub(b, a, s);
> +}
> +
> +static uint32_t float32_rsub(uint32_t a, uint32_t b, float_status *s)
> +{
> +    return float32_sub(b, a, s);
> +}
> +
> +static uint64_t float64_rsub(uint64_t a, uint64_t b, float_status *s)
> +{
> +    return float64_sub(b, a, s);
> +}
> +
> +RVVCALL(OPFVF2, vfrsub_vf_h, OP_UUU_H, H2, H2, float16_rsub)
> +RVVCALL(OPFVF2, vfrsub_vf_w, OP_UUU_W, H4, H4, float32_rsub)
> +RVVCALL(OPFVF2, vfrsub_vf_d, OP_UUU_D, H8, H8, float64_rsub)
> +GEN_VEXT_VF(vfrsub_vf_h, 2, 2, clearh)
> +GEN_VEXT_VF(vfrsub_vf_w, 4, 4, clearl)
> +GEN_VEXT_VF(vfrsub_vf_d, 8, 8, clearq)
> --
> 2.23.0
>


  reply	other threads:[~2020-04-17 22:17 UTC|newest]

Thread overview: 77+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-30 15:35 [PATCH v7 00/61] target/riscv: support vector extension v0.7.1 LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 01/61] target/riscv: add vector extension field in CPURISCVState LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 02/61] target/riscv: implementation-defined constant parameters LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 03/61] target/riscv: support vector extension csr LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 04/61] target/riscv: add vector configure instruction LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 05/61] target/riscv: add an internals.h header LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 06/61] target/riscv: add vector stride load and store instructions LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 07/61] target/riscv: add vector index " LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 08/61] target/riscv: add fault-only-first unit stride load LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 09/61] target/riscv: add vector amo operations LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 10/61] target/riscv: vector single-width integer add and subtract LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 11/61] target/riscv: vector widening " LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 12/61] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 13/61] target/riscv: vector bitwise logical instructions LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 14/61] target/riscv: vector single-width bit shift instructions LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 15/61] target/riscv: vector narrowing integer right " LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 16/61] target/riscv: vector integer comparison instructions LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 17/61] target/riscv: vector integer min/max instructions LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 18/61] target/riscv: vector single-width integer multiply instructions LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 19/61] target/riscv: vector integer divide instructions LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 20/61] target/riscv: vector widening integer multiply instructions LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 21/61] target/riscv: vector single-width integer multiply-add instructions LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 22/61] target/riscv: vector widening " LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 23/61] target/riscv: vector integer merge and move instructions LIU Zhiwei
2020-03-30 15:35 ` [PATCH v7 24/61] target/riscv: vector single-width saturating add and subtract LIU Zhiwei
2020-03-30 16:46   ` Alistair Francis
2020-03-30 15:35 ` [PATCH v7 25/61] target/riscv: vector single-width averaging " LIU Zhiwei
2020-04-02 17:23   ` Alistair Francis
2020-03-30 15:35 ` [PATCH v7 26/61] target/riscv: vector single-width fractional multiply with rounding and saturation LIU Zhiwei
2020-04-02 17:25   ` Alistair Francis
2020-03-30 15:35 ` [PATCH v7 27/61] target/riscv: vector widening saturating scaled multiply-add LIU Zhiwei
2020-04-02 22:53   ` Alistair Francis
2020-03-30 15:36 ` [PATCH v7 28/61] target/riscv: vector single-width scaling shift instructions LIU Zhiwei
2020-04-17 21:55   ` Alistair Francis
2020-03-30 15:36 ` [PATCH v7 29/61] target/riscv: vector narrowing fixed-point clip instructions LIU Zhiwei
2020-04-17 21:45   ` Alistair Francis
2020-03-30 15:36 ` [PATCH v7 30/61] target/riscv: vector single-width floating-point add/subtract instructions LIU Zhiwei
2020-04-17 22:07   ` Alistair Francis [this message]
2020-03-30 15:36 ` [PATCH v7 31/61] target/riscv: vector widening " LIU Zhiwei
2020-04-17 22:01   ` Alistair Francis
2020-03-30 15:36 ` [PATCH v7 32/61] target/riscv: vector single-width floating-point multiply/divide instructions LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 33/61] target/riscv: vector widening floating-point multiply LIU Zhiwei
2020-04-17 21:46   ` Alistair Francis
2020-03-30 15:36 ` [PATCH v7 34/61] target/riscv: vector single-width floating-point fused multiply-add instructions LIU Zhiwei
2020-04-17 22:02   ` Alistair Francis
2020-03-30 15:36 ` [PATCH v7 35/61] target/riscv: vector widening " LIU Zhiwei
2020-04-17 22:11   ` Alistair Francis
2020-03-30 15:36 ` [PATCH v7 36/61] target/riscv: vector floating-point square-root instruction LIU Zhiwei
2020-04-17 22:13   ` Alistair Francis
2020-03-30 15:36 ` [PATCH v7 37/61] target/riscv: vector floating-point min/max instructions LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 38/61] target/riscv: vector floating-point sign-injection instructions LIU Zhiwei
2020-04-17 22:14   ` Alistair Francis
2020-03-30 15:36 ` [PATCH v7 39/61] target/riscv: vector floating-point compare instructions LIU Zhiwei
2020-04-17 22:32   ` Alistair Francis
2020-03-30 15:36 ` [PATCH v7 40/61] target/riscv: vector floating-point classify instructions LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 41/61] target/riscv: vector floating-point merge instructions LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 42/61] target/riscv: vector floating-point/integer type-convert instructions LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 43/61] target/riscv: widening " LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 44/61] target/riscv: narrowing " LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 45/61] target/riscv: vector single-width integer reduction instructions LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 46/61] target/riscv: vector wideing " LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 47/61] target/riscv: vector single-width floating-point " LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 48/61] target/riscv: vector widening " LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 49/61] target/riscv: vector mask-register logical instructions LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 50/61] target/riscv: vector mask population count vmpopc LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 51/61] target/riscv: vmfirst find-first-set mask bit LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 52/61] target/riscv: set-X-first " LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 53/61] target/riscv: vector iota instruction LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 54/61] target/riscv: vector element index instruction LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 55/61] target/riscv: integer extract instruction LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 56/61] target/riscv: integer scalar move instruction LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 57/61] target/riscv: floating-point scalar move instructions LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 58/61] target/riscv: vector slide instructions LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 59/61] target/riscv: vector register gather instruction LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 60/61] target/riscv: vector compress instruction LIU Zhiwei
2020-03-30 15:36 ` [PATCH v7 61/61] target/riscv: configure and turn on vector extension from command line LIU Zhiwei
2020-03-30 23:37 ` [PATCH v7 00/61] target/riscv: support vector extension v0.7.1 no-reply

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=CAKmqyKNg9oGynDHAMcmOZ_RtNpRNnxJa1tOSRDWVA0zqkcxnoA@mail.gmail.com \
    --to=alistair23@gmail.com \
    --cc=chihmin.chao@sifive.com \
    --cc=guoren@linux.alibaba.com \
    --cc=palmer@dabbelt.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    --cc=richard.henderson@linaro.org \
    --cc=wenmeng_zhang@c-sky.com \
    --cc=wxy194768@alibaba-inc.com \
    --cc=zhiwei_liu@c-sky.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).