* [PATCH v7 1/8] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
2024-09-19 5:50 [PATCH v7 0/8] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
@ 2024-09-19 5:50 ` LIU Zhiwei
2024-09-19 5:50 ` [PATCH v7 2/8] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32 LIU Zhiwei
` (7 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: LIU Zhiwei @ 2024-09-19 5:50 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, dbarboza, liwei1518,
bmeng.cn, zhiwei_liu, TANG Tiancheng
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
RV32 OpenSBI need a fw_dynamic_info parameter with 32-bit fields instead
of target_ulong.
In RV64 QEMU, target_ulong is 64. So it is not right for booting RV32 OpenSBI.
We create a fw_dynmaic_info32 struct for this purpose.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/boot.c | 35 ++++++++++++++++++++++-----------
hw/riscv/sifive_u.c | 3 ++-
include/hw/riscv/boot.h | 4 +++-
include/hw/riscv/boot_opensbi.h | 29 +++++++++++++++++++++++++++
4 files changed, 57 insertions(+), 14 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 47281ca853..1a2c1ff9e0 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -342,27 +342,33 @@ void riscv_load_fdt(hwaddr fdt_addr, void *fdt)
rom_ptr_for_as(&address_space_memory, fdt_addr, fdtsize));
}
-void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
- hwaddr rom_size, uint32_t reset_vec_size,
+void riscv_rom_copy_firmware_info(MachineState *machine,
+ RISCVHartArrayState *harts,
+ hwaddr rom_base, hwaddr rom_size,
+ uint32_t reset_vec_size,
uint64_t kernel_entry)
{
+ struct fw_dynamic_info32 dinfo32;
struct fw_dynamic_info dinfo;
size_t dinfo_len;
- if (sizeof(dinfo.magic) == 4) {
- dinfo.magic = cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE);
- dinfo.version = cpu_to_le32(FW_DYNAMIC_INFO_VERSION);
- dinfo.next_mode = cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S);
- dinfo.next_addr = cpu_to_le32(kernel_entry);
+ if (riscv_is_32bit(harts)) {
+ dinfo32.magic = cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE);
+ dinfo32.version = cpu_to_le32(FW_DYNAMIC_INFO_VERSION);
+ dinfo32.next_mode = cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S);
+ dinfo32.next_addr = cpu_to_le32(kernel_entry);
+ dinfo32.options = 0;
+ dinfo32.boot_hart = 0;
+ dinfo_len = sizeof(dinfo32);
} else {
dinfo.magic = cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE);
dinfo.version = cpu_to_le64(FW_DYNAMIC_INFO_VERSION);
dinfo.next_mode = cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S);
dinfo.next_addr = cpu_to_le64(kernel_entry);
+ dinfo.options = 0;
+ dinfo.boot_hart = 0;
+ dinfo_len = sizeof(dinfo);
}
- dinfo.options = 0;
- dinfo.boot_hart = 0;
- dinfo_len = sizeof(dinfo);
/**
* copy the dynamic firmware info. This information is specific to
@@ -374,7 +380,10 @@ void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
exit(1);
}
- rom_add_blob_fixed_as("mrom.finfo", &dinfo, dinfo_len,
+ rom_add_blob_fixed_as("mrom.finfo",
+ riscv_is_32bit(harts) ?
+ (void *)&dinfo32 : (void *)&dinfo,
+ dinfo_len,
rom_base + reset_vec_size,
&address_space_memory);
}
@@ -430,7 +439,9 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
}
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
rom_base, &address_space_memory);
- riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec),
+ riscv_rom_copy_firmware_info(machine, harts,
+ rom_base, rom_size,
+ sizeof(reset_vec),
kernel_entry);
}
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index af5f923f54..5010c3eadb 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -646,7 +646,8 @@ static void sifive_u_machine_init(MachineState *machine)
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory);
- riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base,
+ riscv_rom_copy_firmware_info(machine, &s->soc.u_cpus,
+ memmap[SIFIVE_U_DEV_MROM].base,
memmap[SIFIVE_U_DEV_MROM].size,
sizeof(reset_vec), kernel_entry);
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index a2e4ae9cb0..806256d23f 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -56,7 +56,9 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts
hwaddr rom_base, hwaddr rom_size,
uint64_t kernel_entry,
uint64_t fdt_load_addr);
-void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
+void riscv_rom_copy_firmware_info(MachineState *machine,
+ RISCVHartArrayState *harts,
+ hwaddr rom_base,
hwaddr rom_size,
uint32_t reset_vec_size,
uint64_t kernel_entry);
diff --git a/include/hw/riscv/boot_opensbi.h b/include/hw/riscv/boot_opensbi.h
index 1b749663dc..18664a174b 100644
--- a/include/hw/riscv/boot_opensbi.h
+++ b/include/hw/riscv/boot_opensbi.h
@@ -58,4 +58,33 @@ struct fw_dynamic_info {
target_long boot_hart;
};
+/** Representation dynamic info passed by previous booting stage */
+struct fw_dynamic_info32 {
+ /** Info magic */
+ int32_t magic;
+ /** Info version */
+ int32_t version;
+ /** Next booting stage address */
+ int32_t next_addr;
+ /** Next booting stage mode */
+ int32_t next_mode;
+ /** Options for OpenSBI library */
+ int32_t options;
+ /**
+ * Preferred boot HART id
+ *
+ * It is possible that the previous booting stage uses same link
+ * address as the FW_DYNAMIC firmware. In this case, the relocation
+ * lottery mechanism can potentially overwrite the previous booting
+ * stage while other HARTs are still running in the previous booting
+ * stage leading to boot-time crash. To avoid this boot-time crash,
+ * the previous booting stage can specify last HART that will jump
+ * to the FW_DYNAMIC firmware as the preferred boot HART.
+ *
+ * To avoid specifying a preferred boot HART, the previous booting
+ * stage can set it to -1UL which will force the FW_DYNAMIC firmware
+ * to use the relocation lottery mechanism.
+ */
+ int32_t boot_hart;
+};
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v7 2/8] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
2024-09-19 5:50 [PATCH v7 0/8] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
2024-09-19 5:50 ` [PATCH v7 1/8] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI LIU Zhiwei
@ 2024-09-19 5:50 ` LIU Zhiwei
2024-09-19 5:50 ` [PATCH v7 3/8] target/riscv: Correct SXL return value for RV32 in RV64 QEMU LIU Zhiwei
` (6 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: LIU Zhiwei @ 2024-09-19 5:50 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, dbarboza, liwei1518,
bmeng.cn, zhiwei_liu, TANG Tiancheng
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Ensure pmp_size is correctly determined using mxl for RV32
in RV64 QEMU.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 9eea397e72..5e74b7220f 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -326,7 +326,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr,
*/
pmp_size = -(addr | TARGET_PAGE_MASK);
} else {
- pmp_size = sizeof(target_ulong);
+ pmp_size = 2 << riscv_cpu_mxl(env);
}
} else {
pmp_size = size;
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v7 3/8] target/riscv: Correct SXL return value for RV32 in RV64 QEMU
2024-09-19 5:50 [PATCH v7 0/8] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
2024-09-19 5:50 ` [PATCH v7 1/8] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI LIU Zhiwei
2024-09-19 5:50 ` [PATCH v7 2/8] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32 LIU Zhiwei
@ 2024-09-19 5:50 ` LIU Zhiwei
2024-09-19 5:50 ` [PATCH v7 4/8] target/riscv: Detect sxl to set bit width for RV32 in RV64 LIU Zhiwei
` (5 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: LIU Zhiwei @ 2024-09-19 5:50 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, dbarboza, liwei1518,
bmeng.cn, zhiwei_liu, TANG Tiancheng
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Ensure that riscv_cpu_sxl returns MXL_RV32 when runningRV32 in an
RV64 QEMU.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Fixes: 05e6ca5e156 ("target/riscv: Ignore reserved bits in PTE for RV64")
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1619c3acb6..a63a29744c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -709,8 +709,11 @@ static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
#ifdef CONFIG_USER_ONLY
return env->misa_mxl;
#else
- return get_field(env->mstatus, MSTATUS64_SXL);
+ if (env->misa_mxl != MXL_RV32) {
+ return get_field(env->mstatus, MSTATUS64_SXL);
+ }
#endif
+ return MXL_RV32;
}
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v7 4/8] target/riscv: Detect sxl to set bit width for RV32 in RV64
2024-09-19 5:50 [PATCH v7 0/8] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
` (2 preceding siblings ...)
2024-09-19 5:50 ` [PATCH v7 3/8] target/riscv: Correct SXL return value for RV32 in RV64 QEMU LIU Zhiwei
@ 2024-09-19 5:50 ` LIU Zhiwei
2024-09-19 5:50 ` [PATCH v7 5/8] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU LIU Zhiwei
` (4 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: LIU Zhiwei @ 2024-09-19 5:50 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, dbarboza, liwei1518,
bmeng.cn, zhiwei_liu, TANG Tiancheng
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Ensure correct bit width based on sxl when running RV32 on RV64 QEMU.
This is required as MMU address translations run in S-mode.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 395a1d9140..521d49112f 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -890,12 +890,14 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
CPUState *cs = env_cpu(env);
int va_bits = PGSHIFT + levels * ptidxbits + widened;
+ int sxlen = 16 << riscv_cpu_sxl(env);
+ int sxlen_bytes = sxlen / 8;
if (first_stage == true) {
target_ulong mask, masked_msbs;
- if (TARGET_LONG_BITS > (va_bits - 1)) {
- mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
+ if (sxlen > (va_bits - 1)) {
+ mask = (1L << (sxlen - (va_bits - 1))) - 1;
} else {
mask = 0;
}
@@ -964,7 +966,7 @@ restart:
int pmp_prot;
int pmp_ret = get_physical_address_pmp(env, &pmp_prot, pte_addr,
- sizeof(target_ulong),
+ sxlen_bytes,
MMU_DATA_LOAD, PRV_S);
if (pmp_ret != TRANSLATE_SUCCESS) {
return TRANSLATE_PMP_FAIL;
@@ -1116,7 +1118,7 @@ restart:
* it is no longer valid and we must re-walk the page table.
*/
MemoryRegion *mr;
- hwaddr l = sizeof(target_ulong), addr1;
+ hwaddr l = sxlen_bytes, addr1;
mr = address_space_translate(cs->as, pte_addr, &addr1, &l,
false, MEMTXATTRS_UNSPECIFIED);
if (memory_region_is_ram(mr)) {
@@ -1128,7 +1130,12 @@ restart:
*/
*pte_pa = pte = updated_pte;
#else
- target_ulong old_pte = qatomic_cmpxchg(pte_pa, pte, updated_pte);
+ target_ulong old_pte;
+ if (riscv_cpu_sxl(env) == MXL_RV32) {
+ old_pte = qatomic_cmpxchg((uint32_t *)pte_pa, pte, updated_pte);
+ } else {
+ old_pte = qatomic_cmpxchg(pte_pa, pte, updated_pte);
+ }
if (old_pte != pte) {
goto restart;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v7 5/8] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
2024-09-19 5:50 [PATCH v7 0/8] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
` (3 preceding siblings ...)
2024-09-19 5:50 ` [PATCH v7 4/8] target/riscv: Detect sxl to set bit width for RV32 in RV64 LIU Zhiwei
@ 2024-09-19 5:50 ` LIU Zhiwei
2024-09-19 5:50 ` [PATCH v7 6/8] target/riscv: Enable RV32 CPU support " LIU Zhiwei
` (3 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: LIU Zhiwei @ 2024-09-19 5:50 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, dbarboza, liwei1518,
bmeng.cn, zhiwei_liu, TANG Tiancheng
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Ensure mcause high bit is correctly set by using 32-bit width for RV32
mode and 64-bit width for RV64 mode.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 521d49112f..077f6d77c3 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1677,6 +1677,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
target_ulong tinst = 0;
target_ulong htval = 0;
target_ulong mtval2 = 0;
+ int sxlen = 0;
+ int mxlen = 0;
if (!async) {
/* set tval to badaddr for traps with address information */
@@ -1803,7 +1805,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
s = set_field(s, MSTATUS_SPP, env->priv);
s = set_field(s, MSTATUS_SIE, 0);
env->mstatus = s;
- env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));
+ sxlen = 16 << riscv_cpu_sxl(env);
+ env->scause = cause | ((target_ulong)async << (sxlen - 1));
env->sepc = env->pc;
env->stval = tval;
env->htval = htval;
@@ -1834,7 +1837,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
s = set_field(s, MSTATUS_MPP, env->priv);
s = set_field(s, MSTATUS_MIE, 0);
env->mstatus = s;
- env->mcause = cause | ~(((target_ulong)-1) >> async);
+ mxlen = 16 << riscv_cpu_mxl(env);
+ env->mcause = cause | ((target_ulong)async << (mxlen - 1));
env->mepc = env->pc;
env->mtval = tval;
env->mtval2 = mtval2;
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v7 6/8] target/riscv: Enable RV32 CPU support in RV64 QEMU
2024-09-19 5:50 [PATCH v7 0/8] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
` (4 preceding siblings ...)
2024-09-19 5:50 ` [PATCH v7 5/8] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU LIU Zhiwei
@ 2024-09-19 5:50 ` LIU Zhiwei
2024-09-19 5:50 ` [PATCH v7 7/8] target/riscv: Add max32 CPU for " LIU Zhiwei
` (2 subsequent siblings)
8 siblings, 0 replies; 14+ messages in thread
From: LIU Zhiwei @ 2024-09-19 5:50 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, dbarboza, liwei1518,
bmeng.cn, zhiwei_liu, TANG Tiancheng
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Add gdb XML files and adjust CPU initialization to allow running RV32 CPUs
in RV64 QEMU.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
configs/targets/riscv64-softmmu.mak | 2 +-
target/riscv/cpu.c | 16 +++++++++++++---
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/configs/targets/riscv64-softmmu.mak b/configs/targets/riscv64-softmmu.mak
index 917980e63e..6c5de72e03 100644
--- a/configs/targets/riscv64-softmmu.mak
+++ b/configs/targets/riscv64-softmmu.mak
@@ -2,6 +2,6 @@ TARGET_ARCH=riscv64
TARGET_BASE_ARCH=riscv
TARGET_SUPPORTS_MTTCG=y
TARGET_KVM_HAVE_GUEST_DEBUG=y
-TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml
+TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-virtual.xml
# needed by boot.c
TARGET_NEED_FDT=y
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4bda754b01..86ce15252a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -614,7 +614,10 @@ static void rv64e_bare_cpu_init(Object *obj)
riscv_cpu_set_misa_ext(env, RVE);
}
-#else /* !TARGET_RISCV64 */
+#endif /* !TARGET_RISCV64 */
+
+#if defined(TARGET_RISCV32) || \
+ (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
static void rv32_base_cpu_init(Object *obj)
{
@@ -2927,6 +2930,12 @@ static const TypeInfo riscv_cpu_type_infos[] = {
},
#if defined(TARGET_RISCV32)
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV32, riscv_max_cpu_init),
+#elif defined(TARGET_RISCV64)
+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV64, riscv_max_cpu_init),
+#endif
+
+#if defined(TARGET_RISCV32) || \
+ (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, MXL_RV32, rv32_base_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32, rv32_ibex_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32, rv32_sifive_e_cpu_init),
@@ -2934,8 +2943,9 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32, rv32_sifive_u_cpu_init),
DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32I, MXL_RV32, rv32i_bare_cpu_init),
DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32E, MXL_RV32, rv32e_bare_cpu_init),
-#elif defined(TARGET_RISCV64)
- DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV64, riscv_max_cpu_init),
+#endif
+
+#if defined(TARGET_RISCV64)
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, MXL_RV64, rv64_base_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_cpu_init),
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v7 7/8] target/riscv: Add max32 CPU for RV64 QEMU
2024-09-19 5:50 [PATCH v7 0/8] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
` (5 preceding siblings ...)
2024-09-19 5:50 ` [PATCH v7 6/8] target/riscv: Enable RV32 CPU support " LIU Zhiwei
@ 2024-09-19 5:50 ` LIU Zhiwei
2024-09-26 21:54 ` Daniel Henrique Barboza
2024-10-08 0:49 ` Alistair Francis
2024-09-19 5:50 ` [PATCH v7 8/8] tests/avocado: Boot Linux for RV32 cpu on " LIU Zhiwei
2024-10-08 1:17 ` [PATCH v7 0/8] target/riscv: Expose RV32 cpu to " Alistair Francis
8 siblings, 2 replies; 14+ messages in thread
From: LIU Zhiwei @ 2024-09-19 5:50 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, dbarboza, liwei1518,
bmeng.cn, zhiwei_liu
We may need 32-bit max for RV64 QEMU. Thus we add these two CPUs
for RV64 QEMU.
The reason we don't expose them to RV32 QEMU is that we already have
max cpu with the same configuration. Another reason is that we want
to follow the RISC-V custom where addw instruction doesn't exist in
RV32 CPU.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Suggested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 12 +++++++-----
2 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 4464c0fd7a..62115375cd 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -30,6 +30,7 @@
#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
#define TYPE_RISCV_CPU_MAX RISCV_CPU_TYPE_NAME("max")
+#define TYPE_RISCV_CPU_MAX32 RISCV_CPU_TYPE_NAME("max32")
#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 86ce15252a..baf8fba467 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -448,11 +448,9 @@ static void riscv_max_cpu_init(Object *obj)
env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
-#ifdef TARGET_RISCV32
- set_satp_mode_max_supported(cpu, VM_1_10_SV32);
-#else
- set_satp_mode_max_supported(cpu, VM_1_10_SV57);
-#endif
+ set_satp_mode_max_supported(RISCV_CPU(obj),
+ riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ?
+ VM_1_10_SV32 : VM_1_10_SV57);
#endif
}
@@ -2945,6 +2943,10 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32E, MXL_RV32, rv32e_bare_cpu_init),
#endif
+#if (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX32, MXL_RV32, riscv_max_cpu_init),
+#endif
+
#if defined(TARGET_RISCV64)
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, MXL_RV64, rv64_base_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_cpu_init),
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v7 7/8] target/riscv: Add max32 CPU for RV64 QEMU
2024-09-19 5:50 ` [PATCH v7 7/8] target/riscv: Add max32 CPU for " LIU Zhiwei
@ 2024-09-26 21:54 ` Daniel Henrique Barboza
2024-10-08 0:49 ` Alistair Francis
1 sibling, 0 replies; 14+ messages in thread
From: Daniel Henrique Barboza @ 2024-09-26 21:54 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, liwei1518, bmeng.cn
On 9/19/24 2:50 AM, LIU Zhiwei wrote:
> We may need 32-bit max for RV64 QEMU. Thus we add these two CPUs
> for RV64 QEMU.
>
> The reason we don't expose them to RV32 QEMU is that we already have
> max cpu with the same configuration. Another reason is that we want
> to follow the RISC-V custom where addw instruction doesn't exist in
> RV32 CPU.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Suggested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/cpu-qom.h | 1 +
> target/riscv/cpu.c | 12 +++++++-----
> 2 files changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> index 4464c0fd7a..62115375cd 100644
> --- a/target/riscv/cpu-qom.h
> +++ b/target/riscv/cpu-qom.h
> @@ -30,6 +30,7 @@
> #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
>
> #define TYPE_RISCV_CPU_MAX RISCV_CPU_TYPE_NAME("max")
> +#define TYPE_RISCV_CPU_MAX32 RISCV_CPU_TYPE_NAME("max32")
> #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
> #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
> #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 86ce15252a..baf8fba467 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -448,11 +448,9 @@ static void riscv_max_cpu_init(Object *obj)
>
> env->priv_ver = PRIV_VERSION_LATEST;
> #ifndef CONFIG_USER_ONLY
> -#ifdef TARGET_RISCV32
> - set_satp_mode_max_supported(cpu, VM_1_10_SV32);
> -#else
> - set_satp_mode_max_supported(cpu, VM_1_10_SV57);
> -#endif
> + set_satp_mode_max_supported(RISCV_CPU(obj),
> + riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ?
> + VM_1_10_SV32 : VM_1_10_SV57);
> #endif
> }
>
> @@ -2945,6 +2943,10 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32E, MXL_RV32, rv32e_bare_cpu_init),
> #endif
>
> +#if (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
> + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX32, MXL_RV32, riscv_max_cpu_init),
> +#endif
> +
> #if defined(TARGET_RISCV64)
> DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, MXL_RV64, rv64_base_cpu_init),
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_cpu_init),
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v7 7/8] target/riscv: Add max32 CPU for RV64 QEMU
2024-09-19 5:50 ` [PATCH v7 7/8] target/riscv: Add max32 CPU for " LIU Zhiwei
2024-09-26 21:54 ` Daniel Henrique Barboza
@ 2024-10-08 0:49 ` Alistair Francis
1 sibling, 0 replies; 14+ messages in thread
From: Alistair Francis @ 2024-10-08 0:49 UTC (permalink / raw)
To: LIU Zhiwei
Cc: qemu-devel, qemu-riscv, palmer, alistair.francis, dbarboza,
liwei1518, bmeng.cn
On Thu, Sep 19, 2024 at 3:56 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>
> We may need 32-bit max for RV64 QEMU. Thus we add these two CPUs
> for RV64 QEMU.
>
> The reason we don't expose them to RV32 QEMU is that we already have
> max cpu with the same configuration. Another reason is that we want
> to follow the RISC-V custom where addw instruction doesn't exist in
> RV32 CPU.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Suggested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu-qom.h | 1 +
> target/riscv/cpu.c | 12 +++++++-----
> 2 files changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> index 4464c0fd7a..62115375cd 100644
> --- a/target/riscv/cpu-qom.h
> +++ b/target/riscv/cpu-qom.h
> @@ -30,6 +30,7 @@
> #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
>
> #define TYPE_RISCV_CPU_MAX RISCV_CPU_TYPE_NAME("max")
> +#define TYPE_RISCV_CPU_MAX32 RISCV_CPU_TYPE_NAME("max32")
> #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
> #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
> #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128")
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 86ce15252a..baf8fba467 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -448,11 +448,9 @@ static void riscv_max_cpu_init(Object *obj)
>
> env->priv_ver = PRIV_VERSION_LATEST;
> #ifndef CONFIG_USER_ONLY
> -#ifdef TARGET_RISCV32
> - set_satp_mode_max_supported(cpu, VM_1_10_SV32);
> -#else
> - set_satp_mode_max_supported(cpu, VM_1_10_SV57);
> -#endif
> + set_satp_mode_max_supported(RISCV_CPU(obj),
> + riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ?
> + VM_1_10_SV32 : VM_1_10_SV57);
> #endif
> }
>
> @@ -2945,6 +2943,10 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32E, MXL_RV32, rv32e_bare_cpu_init),
> #endif
>
> +#if (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
> + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX32, MXL_RV32, riscv_max_cpu_init),
> +#endif
> +
> #if defined(TARGET_RISCV64)
> DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, MXL_RV64, rv64_base_cpu_init),
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_cpu_init),
> --
> 2.43.0
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v7 8/8] tests/avocado: Boot Linux for RV32 cpu on RV64 QEMU
2024-09-19 5:50 [PATCH v7 0/8] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
` (6 preceding siblings ...)
2024-09-19 5:50 ` [PATCH v7 7/8] target/riscv: Add max32 CPU for " LIU Zhiwei
@ 2024-09-19 5:50 ` LIU Zhiwei
2024-09-26 21:55 ` Daniel Henrique Barboza
2024-10-08 0:49 ` Alistair Francis
2024-10-08 1:17 ` [PATCH v7 0/8] target/riscv: Expose RV32 cpu to " Alistair Francis
8 siblings, 2 replies; 14+ messages in thread
From: LIU Zhiwei @ 2024-09-19 5:50 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, dbarboza, liwei1518,
bmeng.cn, zhiwei_liu
make check-avocado AVOCADO_TESTS=tests/avocado/tuxrun_baselines.py: \
TuxRunBaselineTest:test_riscv64_rv32
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Suggested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
tests/avocado/tuxrun_baselines.py | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/tests/avocado/tuxrun_baselines.py b/tests/avocado/tuxrun_baselines.py
index 736e4aa289..589c7f254b 100644
--- a/tests/avocado/tuxrun_baselines.py
+++ b/tests/avocado/tuxrun_baselines.py
@@ -533,6 +533,22 @@ def test_riscv64_maxcpu(self):
self.common_tuxrun(csums=sums)
+ def test_riscv64_rv32(self):
+ """
+ :avocado: tags=arch:riscv64
+ :avocado: tags=machine:virt
+ :avocado: tags=tuxboot:riscv32
+ :avocado: tags=cpu:rv32
+ """
+ sums = { "Image" :
+ "89599407d7334de629a40e7ad6503c73670359eb5f5ae9d686353a3d6deccbd5",
+ "fw_jump.elf" :
+ "f2ef28a0b77826f79d085d3e4aa686f1159b315eff9099a37046b18936676985",
+ "rootfs.ext4.zst" :
+ "7168d296d0283238ea73cd5a775b3dd608e55e04c7b92b76ecce31bb13108cba" }
+
+ self.common_tuxrun(csums=sums)
+
def test_s390(self):
"""
:avocado: tags=arch:s390x
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v7 8/8] tests/avocado: Boot Linux for RV32 cpu on RV64 QEMU
2024-09-19 5:50 ` [PATCH v7 8/8] tests/avocado: Boot Linux for RV32 cpu on " LIU Zhiwei
@ 2024-09-26 21:55 ` Daniel Henrique Barboza
2024-10-08 0:49 ` Alistair Francis
1 sibling, 0 replies; 14+ messages in thread
From: Daniel Henrique Barboza @ 2024-09-26 21:55 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel
Cc: qemu-riscv, palmer, alistair.francis, liwei1518, bmeng.cn
On 9/19/24 2:50 AM, LIU Zhiwei wrote:
> make check-avocado AVOCADO_TESTS=tests/avocado/tuxrun_baselines.py: \
> TuxRunBaselineTest:test_riscv64_rv32
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Suggested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> tests/avocado/tuxrun_baselines.py | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/tests/avocado/tuxrun_baselines.py b/tests/avocado/tuxrun_baselines.py
> index 736e4aa289..589c7f254b 100644
> --- a/tests/avocado/tuxrun_baselines.py
> +++ b/tests/avocado/tuxrun_baselines.py
> @@ -533,6 +533,22 @@ def test_riscv64_maxcpu(self):
>
> self.common_tuxrun(csums=sums)
>
> + def test_riscv64_rv32(self):
> + """
> + :avocado: tags=arch:riscv64
> + :avocado: tags=machine:virt
> + :avocado: tags=tuxboot:riscv32
> + :avocado: tags=cpu:rv32
> + """
> + sums = { "Image" :
> + "89599407d7334de629a40e7ad6503c73670359eb5f5ae9d686353a3d6deccbd5",
> + "fw_jump.elf" :
> + "f2ef28a0b77826f79d085d3e4aa686f1159b315eff9099a37046b18936676985",
> + "rootfs.ext4.zst" :
> + "7168d296d0283238ea73cd5a775b3dd608e55e04c7b92b76ecce31bb13108cba" }
> +
> + self.common_tuxrun(csums=sums)
> +
> def test_s390(self):
> """
> :avocado: tags=arch:s390x
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v7 8/8] tests/avocado: Boot Linux for RV32 cpu on RV64 QEMU
2024-09-19 5:50 ` [PATCH v7 8/8] tests/avocado: Boot Linux for RV32 cpu on " LIU Zhiwei
2024-09-26 21:55 ` Daniel Henrique Barboza
@ 2024-10-08 0:49 ` Alistair Francis
1 sibling, 0 replies; 14+ messages in thread
From: Alistair Francis @ 2024-10-08 0:49 UTC (permalink / raw)
To: LIU Zhiwei
Cc: qemu-devel, qemu-riscv, palmer, alistair.francis, dbarboza,
liwei1518, bmeng.cn
On Thu, Sep 19, 2024 at 3:57 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>
> make check-avocado AVOCADO_TESTS=tests/avocado/tuxrun_baselines.py: \
> TuxRunBaselineTest:test_riscv64_rv32
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Suggested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> tests/avocado/tuxrun_baselines.py | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/tests/avocado/tuxrun_baselines.py b/tests/avocado/tuxrun_baselines.py
> index 736e4aa289..589c7f254b 100644
> --- a/tests/avocado/tuxrun_baselines.py
> +++ b/tests/avocado/tuxrun_baselines.py
> @@ -533,6 +533,22 @@ def test_riscv64_maxcpu(self):
>
> self.common_tuxrun(csums=sums)
>
> + def test_riscv64_rv32(self):
> + """
> + :avocado: tags=arch:riscv64
> + :avocado: tags=machine:virt
> + :avocado: tags=tuxboot:riscv32
> + :avocado: tags=cpu:rv32
> + """
> + sums = { "Image" :
> + "89599407d7334de629a40e7ad6503c73670359eb5f5ae9d686353a3d6deccbd5",
> + "fw_jump.elf" :
> + "f2ef28a0b77826f79d085d3e4aa686f1159b315eff9099a37046b18936676985",
> + "rootfs.ext4.zst" :
> + "7168d296d0283238ea73cd5a775b3dd608e55e04c7b92b76ecce31bb13108cba" }
> +
> + self.common_tuxrun(csums=sums)
> +
> def test_s390(self):
> """
> :avocado: tags=arch:s390x
> --
> 2.43.0
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v7 0/8] target/riscv: Expose RV32 cpu to RV64 QEMU
2024-09-19 5:50 [PATCH v7 0/8] target/riscv: Expose RV32 cpu to RV64 QEMU LIU Zhiwei
` (7 preceding siblings ...)
2024-09-19 5:50 ` [PATCH v7 8/8] tests/avocado: Boot Linux for RV32 cpu on " LIU Zhiwei
@ 2024-10-08 1:17 ` Alistair Francis
8 siblings, 0 replies; 14+ messages in thread
From: Alistair Francis @ 2024-10-08 1:17 UTC (permalink / raw)
To: LIU Zhiwei
Cc: qemu-devel, qemu-riscv, palmer, alistair.francis, dbarboza,
liwei1518, bmeng.cn, TANG Tiancheng
On Thu, Sep 19, 2024 at 3:53 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>
> From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
>
> This patch set aims to expose 32-bit RISC-V cpu to RV64 QEMU. Thus
> qemu-system-riscv64 can directly boot a RV32 Linux.
>
> This patch set has been tested with 6.9.0 Linux Image.
> And add an avocado tuxrun test in tests/avocado.
>
> v7:
> Remove cpu of "any".
>
> v6:
> Use TUXRUN test case instead of boot_linux_console
> Add any32 and max32 cpu for RV64 QEMU
>
> v5:
> Rebase to master and add tags
>
> v4:
> Drop UL completely in PATCH v3 2/7, 4/7, 5/7.
> Avocado: Add "if=none" to "-drive" option in QEMU command line
>
> v3:
> Rebase to the master branch
>
> v2:
> Remove the line that was inadvertently left in PATCH v1 4/6.
> Add an avocado test.
>
> v1:
> https://mail.gnu.org/archive/html/qemu-riscv/2024-06/msg00501.html
>
> LIU Zhiwei (2):
> target/riscv: Add max32 CPU for RV64 QEMU
> tests/avocado: Boot Linux for RV32 cpu on RV64 QEMU
>
> TANG Tiancheng (6):
> target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
> target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
> target/riscv: Correct SXL return value for RV32 in RV64 QEMU
> target/riscv: Detect sxl to set bit width for RV32 in RV64
> target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
> target/riscv: Enable RV32 CPU support in RV64 QEMU
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> configs/targets/riscv64-softmmu.mak | 2 +-
> hw/riscv/boot.c | 35 +++++++++++++++++++----------
> hw/riscv/sifive_u.c | 3 ++-
> include/hw/riscv/boot.h | 4 +++-
> include/hw/riscv/boot_opensbi.h | 29 ++++++++++++++++++++++++
> target/riscv/cpu-qom.h | 1 +
> target/riscv/cpu.c | 28 ++++++++++++++++-------
> target/riscv/cpu.h | 5 ++++-
> target/riscv/cpu_helper.c | 25 +++++++++++++++------
> target/riscv/pmp.c | 2 +-
> tests/avocado/tuxrun_baselines.py | 16 +++++++++++++
> 11 files changed, 118 insertions(+), 32 deletions(-)
>
> --
> 2.43.0
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread