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Thu, 03 Apr 2025 20:22:51 -0700 (PDT) MIME-Version: 1.0 References: <20250321155925.96626-1-philmd@linaro.org> <20250321155925.96626-2-philmd@linaro.org> <2650b68f-e705-4994-9791-0bf8b2e01d74@linaro.org> <43e170ad-d4e3-489d-a049-22361cd34f13@linaro.org> <90049822-b71a-4120-9537-7d43caf44f83@linaro.org> In-Reply-To: <90049822-b71a-4120-9537-7d43caf44f83@linaro.org> From: Alistair Francis Date: Fri, 4 Apr 2025 13:22:25 +1000 X-Gm-Features: ATxdqUG_8ZIFOQrkqkQx85njyB1WtetoFPJlwcOXe0nQVRI2KqAtwFXtZREabPA Message-ID: Subject: Re: [PATCH-for-10.1 1/4] target/riscv: Restrict RV128 MTTCG check on system emulation To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: Richard Henderson , qemu-devel@nongnu.org, Alexandre Ghiti , Anton Johansson , Pierrick Bouvier , Paolo Bonzini , qemu-riscv , Frank Chang , Bin Meng , Andrew Jones , Palmer Dabbelt Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::a36; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa36.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Apr 3, 2025 at 12:41=E2=80=AFAM Philippe Mathieu-Daud=C3=A9 wrote: > > On 2/4/25 16:25, Philippe Mathieu-Daud=C3=A9 wrote: > > On 23/3/25 19:08, Richard Henderson wrote: > >> On 3/21/25 08:59, Philippe Mathieu-Daud=C3=A9 wrote: > >>> Multi-threaded TCG only concerns system emulation. > >> > >> That's not really true. User emulation simply has no option to > >> run in a single-threaded context. > >> > >> I really don't think we should allow RV128 in user-mode at all. > >> Certainly not until there's a kernel abi for it. > > > > It seems to be safe since commit 905b9fcde1f ("target/riscv: Replace > > is_32bit with get_xl/get_xlen"): > > > > #ifdef TARGET_RISCV32 > > #define get_xl(ctx) MXL_RV32 > > #elif defined(CONFIG_USER_ONLY) > > #define get_xl(ctx) MXL_RV64 > > #else > > #define get_xl(ctx) ((ctx)->xl) > > #endif > > > > Should we undefine MXL_RV128 on user-mode? > > Indeed the CPU is exposed on user-mode... > > $ qemu-riscv64 -cpu help > Available CPUs: > max > rv64 > rv64e > rv64i > rva22s64 > rva22u64 > rva23s64 > rva23u64 > shakti-c > sifive-e51 > sifive-u54 > thead-c906 > tt-ascalon > veyron-v1 > x-rv128 <--------- > xiangshan-nanhu > > Per commit 6df3747a274 ("riscv: Introduce satp mode hw > capabilities") I wonder if this is expected. We probably didn't really think about it at the time. I agree that we don't need it > > Anyhow, I'll post a patch disabling it as: Thanks Alistair > > -- >8 -- > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 430b02d2a58..33abcef0073 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -699,3 +699,3 @@ static void rv64_xiangshan_nanhu_cpu_init(Object *obj= ) > > -#ifdef CONFIG_TCG > +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) > static void rv128_base_cpu_init(Object *obj) > @@ -710,7 +710,6 @@ static void rv128_base_cpu_init(Object *obj) > env->priv_ver =3D PRIV_VERSION_LATEST; > -#ifndef CONFIG_USER_ONLY > + > set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); > -#endif > } > -#endif /* CONFIG_TCG */ > +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ > > @@ -3257,3 +3256,3 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { > MXL_RV64, > rv64_xiangshan_nanhu_cpu_init), > -#ifdef CONFIG_TCG > +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) > DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, > rv128_base_cpu_init), > > --- >