* [PATCH] hw/riscv/sifive_e: Fix inheritance of SiFiveEState
@ 2022-09-22 7:52 Bernhard Beschow
2022-09-22 7:58 ` Frank Chang
2022-09-23 3:59 ` Alistair Francis
0 siblings, 2 replies; 3+ messages in thread
From: Bernhard Beschow @ 2022-09-22 7:52 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-stable, qemu-riscv, Alistair Francis, Palmer Dabbelt,
Bin Meng, Bernhard Beschow, Alistair Francis,
Philippe Mathieu-Daudé
SiFiveEState inherits from SysBusDevice while it's TypeInfo claims it to
inherit from TYPE_MACHINE. This is an inconsistency which can cause
undefined behavior such as memory corruption.
Change SiFiveEState to inherit from MachineState since it is registered
as a machine.
Fixes: 0869490b1c ("riscv: sifive_e: Manually define the machine")
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/riscv/sifive_e.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
index 83604da805..d738745925 100644
--- a/include/hw/riscv/sifive_e.h
+++ b/include/hw/riscv/sifive_e.h
@@ -22,6 +22,7 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_cpu.h"
#include "hw/gpio/sifive_gpio.h"
+#include "hw/boards.h"
#define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
#define RISCV_E_SOC(obj) \
@@ -41,7 +42,7 @@ typedef struct SiFiveESoCState {
typedef struct SiFiveEState {
/*< private >*/
- SysBusDevice parent_obj;
+ MachineState parent_obj;
/*< public >*/
SiFiveESoCState soc;
--
2.37.3
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] hw/riscv/sifive_e: Fix inheritance of SiFiveEState
2022-09-22 7:52 [PATCH] hw/riscv/sifive_e: Fix inheritance of SiFiveEState Bernhard Beschow
@ 2022-09-22 7:58 ` Frank Chang
2022-09-23 3:59 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Frank Chang @ 2022-09-22 7:58 UTC (permalink / raw)
To: Bernhard Beschow
Cc: qemu-devel, qemu-stable, qemu-riscv, Alistair Francis,
Palmer Dabbelt, Bin Meng, Philippe Mathieu-Daudé
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Hi Bernhard,
I think there's already a similar patch for this bug fix:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg905424.html
Regards,
Frank Chang
On Thu, Sep 22, 2022 at 3:53 PM Bernhard Beschow <shentey@gmail.com> wrote:
> SiFiveEState inherits from SysBusDevice while it's TypeInfo claims it to
> inherit from TYPE_MACHINE. This is an inconsistency which can cause
> undefined behavior such as memory corruption.
>
> Change SiFiveEState to inherit from MachineState since it is registered
> as a machine.
>
> Fixes: 0869490b1c ("riscv: sifive_e: Manually define the machine")
>
> Signed-off-by: Bernhard Beschow <shentey@gmail.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> include/hw/riscv/sifive_e.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
> index 83604da805..d738745925 100644
> --- a/include/hw/riscv/sifive_e.h
> +++ b/include/hw/riscv/sifive_e.h
> @@ -22,6 +22,7 @@
> #include "hw/riscv/riscv_hart.h"
> #include "hw/riscv/sifive_cpu.h"
> #include "hw/gpio/sifive_gpio.h"
> +#include "hw/boards.h"
>
> #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
> #define RISCV_E_SOC(obj) \
> @@ -41,7 +42,7 @@ typedef struct SiFiveESoCState {
>
> typedef struct SiFiveEState {
> /*< private >*/
> - SysBusDevice parent_obj;
> + MachineState parent_obj;
>
> /*< public >*/
> SiFiveESoCState soc;
> --
> 2.37.3
>
>
>
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^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] hw/riscv/sifive_e: Fix inheritance of SiFiveEState
2022-09-22 7:52 [PATCH] hw/riscv/sifive_e: Fix inheritance of SiFiveEState Bernhard Beschow
2022-09-22 7:58 ` Frank Chang
@ 2022-09-23 3:59 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2022-09-23 3:59 UTC (permalink / raw)
To: Bernhard Beschow
Cc: qemu-devel@nongnu.org Developers, qemu-stable, open list:RISC-V,
Alistair Francis, Palmer Dabbelt, Bin Meng,
Philippe Mathieu-Daudé
On Thu, Sep 22, 2022 at 5:56 PM Bernhard Beschow <shentey@gmail.com> wrote:
>
> SiFiveEState inherits from SysBusDevice while it's TypeInfo claims it to
> inherit from TYPE_MACHINE. This is an inconsistency which can cause
> undefined behavior such as memory corruption.
>
> Change SiFiveEState to inherit from MachineState since it is registered
> as a machine.
>
> Fixes: 0869490b1c ("riscv: sifive_e: Manually define the machine")
>
> Signed-off-by: Bernhard Beschow <shentey@gmail.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> include/hw/riscv/sifive_e.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h
> index 83604da805..d738745925 100644
> --- a/include/hw/riscv/sifive_e.h
> +++ b/include/hw/riscv/sifive_e.h
> @@ -22,6 +22,7 @@
> #include "hw/riscv/riscv_hart.h"
> #include "hw/riscv/sifive_cpu.h"
> #include "hw/gpio/sifive_gpio.h"
> +#include "hw/boards.h"
>
> #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc"
> #define RISCV_E_SOC(obj) \
> @@ -41,7 +42,7 @@ typedef struct SiFiveESoCState {
>
> typedef struct SiFiveEState {
> /*< private >*/
> - SysBusDevice parent_obj;
> + MachineState parent_obj;
>
> /*< public >*/
> SiFiveESoCState soc;
> --
> 2.37.3
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2022-09-22 7:52 [PATCH] hw/riscv/sifive_e: Fix inheritance of SiFiveEState Bernhard Beschow
2022-09-22 7:58 ` Frank Chang
2022-09-23 3:59 ` Alistair Francis
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