From: Alistair Francis <alistair23@gmail.com>
To: "Loïc Lefort" <loic@rivosinc.com>
Cc: qemu-devel@nongnu.org, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Weiwei Li <liwei1518@gmail.com>,
qemu-riscv@nongnu.org, Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: Re: [PATCH v2 2/5] target/riscv: pmp: move Smepmp operation conversion into a function
Date: Fri, 4 Apr 2025 11:02:02 +1000 [thread overview]
Message-ID: <CAKmqyKNmrdsgMgpUTknjBzN4ubisvBGF-1qATwPh_T2Z5fNu3g@mail.gmail.com> (raw)
In-Reply-To: <20250313193011.720075-3-loic@rivosinc.com>
On Fri, Mar 14, 2025 at 5:33 AM Loïc Lefort <loic@rivosinc.com> wrote:
>
> Signed-off-by: Loïc Lefort <loic@rivosinc.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/pmp.c | 22 ++++++++++++----------
> 1 file changed, 12 insertions(+), 10 deletions(-)
>
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index e1e5ca589e..7d65dc24a5 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -31,6 +31,15 @@ static bool pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
> uint8_t val);
> static uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t addr_index);
>
> +/*
> + * Convert the PMP permissions to match the truth table in the Smepmp spec.
> + */
> +static inline uint8_t pmp_get_smepmp_operation(uint8_t cfg)
> +{
> + return ((cfg & PMP_LOCK) >> 4) | ((cfg & PMP_READ) << 2) |
> + (cfg & PMP_WRITE) | ((cfg & PMP_EXEC) >> 2);
> +}
> +
> /*
> * Accessor method to extract address matching type 'a field' from cfg reg
> */
> @@ -355,16 +364,6 @@ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr,
> const uint8_t a_field =
> pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
>
> - /*
> - * Convert the PMP permissions to match the truth table in the
> - * Smepmp spec.
> - */
> - const uint8_t smepmp_operation =
> - ((env->pmp_state.pmp[i].cfg_reg & PMP_LOCK) >> 4) |
> - ((env->pmp_state.pmp[i].cfg_reg & PMP_READ) << 2) |
> - (env->pmp_state.pmp[i].cfg_reg & PMP_WRITE) |
> - ((env->pmp_state.pmp[i].cfg_reg & PMP_EXEC) >> 2);
> -
> if (((s + e) == 2) && (PMP_AMATCH_OFF != a_field)) {
> /*
> * If the PMP entry is not off and the address is in range,
> @@ -383,6 +382,9 @@ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr,
> /*
> * If mseccfg.MML Bit set, do the enhanced pmp priv check
> */
> + const uint8_t smepmp_operation =
> + pmp_get_smepmp_operation(env->pmp_state.pmp[i].cfg_reg);
> +
> if (mode == PRV_M) {
> switch (smepmp_operation) {
> case 0:
> --
> 2.47.2
>
>
next prev parent reply other threads:[~2025-04-04 1:02 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-13 19:30 [PATCH v2 0/5] target/riscv: Smepmp fixes to match specification Loïc Lefort
2025-03-13 19:30 ` [PATCH v2 1/5] target/riscv: pmp: don't allow RLB to bypass rule privileges Loïc Lefort
2025-03-27 17:30 ` Daniel Henrique Barboza
2025-03-29 8:33 ` LIU Zhiwei
2025-04-04 1:01 ` Alistair Francis
2025-03-13 19:30 ` [PATCH v2 2/5] target/riscv: pmp: move Smepmp operation conversion into a function Loïc Lefort
2025-03-29 8:53 ` LIU Zhiwei
2025-04-04 1:02 ` Alistair Francis [this message]
2025-03-13 19:30 ` [PATCH v2 3/5] target/riscv: pmp: fix checks on writes to pmpcfg in Smepmp MML mode Loïc Lefort
2025-03-29 9:01 ` LIU Zhiwei
2025-03-13 19:30 ` [PATCH v2 4/5] target/riscv: pmp: exit csr writes early if value was not changed Loïc Lefort
2025-03-29 9:03 ` LIU Zhiwei
2025-03-31 9:44 ` Loïc Lefort
2025-03-31 11:31 ` LIU Zhiwei
2025-04-04 1:05 ` Alistair Francis
2025-03-13 19:30 ` [PATCH v2 5/5] target/riscv: pmp: remove redundant check in pmp_is_locked Loïc Lefort
2025-03-29 9:29 ` LIU Zhiwei
2025-04-04 1:06 ` Alistair Francis
2025-03-27 16:47 ` [PATCH v2 0/5] target/riscv: Smepmp fixes to match specification Loïc Lefort
2025-04-04 1:23 ` Alistair Francis
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