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Thu, 03 Apr 2025 18:02:29 -0700 (PDT) MIME-Version: 1.0 References: <20250313193011.720075-1-loic@rivosinc.com> <20250313193011.720075-3-loic@rivosinc.com> In-Reply-To: <20250313193011.720075-3-loic@rivosinc.com> From: Alistair Francis Date: Fri, 4 Apr 2025 11:02:02 +1000 X-Gm-Features: ATxdqUGQ3Vntb97LMfm6TJHP-pPbgkBnEsTf09QesEfd75T0Y7K285JqbW6g35s Message-ID: Subject: Re: [PATCH v2 2/5] target/riscv: pmp: move Smepmp operation conversion into a function To: =?UTF-8?B?TG/Dr2MgTGVmb3J0?= Cc: qemu-devel@nongnu.org, Liu Zhiwei , Weiwei Li , qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Daniel Henrique Barboza Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::a35; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa35.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Mar 14, 2025 at 5:33=E2=80=AFAM Lo=C3=AFc Lefort wrote: > > Signed-off-by: Lo=C3=AFc Lefort > Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > target/riscv/pmp.c | 22 ++++++++++++---------- > 1 file changed, 12 insertions(+), 10 deletions(-) > > diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c > index e1e5ca589e..7d65dc24a5 100644 > --- a/target/riscv/pmp.c > +++ b/target/riscv/pmp.c > @@ -31,6 +31,15 @@ static bool pmp_write_cfg(CPURISCVState *env, uint32_t= addr_index, > uint8_t val); > static uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t addr_index); > > +/* > + * Convert the PMP permissions to match the truth table in the Smepmp sp= ec. > + */ > +static inline uint8_t pmp_get_smepmp_operation(uint8_t cfg) > +{ > + return ((cfg & PMP_LOCK) >> 4) | ((cfg & PMP_READ) << 2) | > + (cfg & PMP_WRITE) | ((cfg & PMP_EXEC) >> 2); > +} > + > /* > * Accessor method to extract address matching type 'a field' from cfg r= eg > */ > @@ -355,16 +364,6 @@ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr a= ddr, > const uint8_t a_field =3D > pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg); > > - /* > - * Convert the PMP permissions to match the truth table in the > - * Smepmp spec. > - */ > - const uint8_t smepmp_operation =3D > - ((env->pmp_state.pmp[i].cfg_reg & PMP_LOCK) >> 4) | > - ((env->pmp_state.pmp[i].cfg_reg & PMP_READ) << 2) | > - (env->pmp_state.pmp[i].cfg_reg & PMP_WRITE) | > - ((env->pmp_state.pmp[i].cfg_reg & PMP_EXEC) >> 2); > - > if (((s + e) =3D=3D 2) && (PMP_AMATCH_OFF !=3D a_field)) { > /* > * If the PMP entry is not off and the address is in range, > @@ -383,6 +382,9 @@ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr ad= dr, > /* > * If mseccfg.MML Bit set, do the enhanced pmp priv chec= k > */ > + const uint8_t smepmp_operation =3D > + pmp_get_smepmp_operation(env->pmp_state.pmp[i].cfg_r= eg); > + > if (mode =3D=3D PRV_M) { > switch (smepmp_operation) { > case 0: > -- > 2.47.2 > >