From: Alistair Francis <alistair23@gmail.com>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: qemu-devel@nongnu.org
Subject: Re: [PATCH 25/27] target/riscv: convert Ventana V1 to RISCVCPUDef
Date: Thu, 24 Apr 2025 10:45:15 +1000 [thread overview]
Message-ID: <CAKmqyKNn3e+YjWCqaUr4GEEUt42jV01mRQpoogtaRUh2c9avcA@mail.gmail.com> (raw)
In-Reply-To: <20250406070254.274797-26-pbonzini@redhat.com>
On Sun, Apr 6, 2025 at 5:04 PM Paolo Bonzini <pbonzini@redhat.com> wrote:
>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 75 ++++++++++++++++++++++------------------------
> 1 file changed, 35 insertions(+), 40 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 616d89be17e..4e4d8ddf5a2 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -500,45 +500,6 @@ static void riscv_register_custom_csrs(RISCVCPU *cpu, const RISCVCSR *csr_list)
> #endif
>
> #if defined(TARGET_RISCV64)
> -static void rv64_veyron_v1_cpu_init(Object *obj)
> -{
> - CPURISCVState *env = &RISCV_CPU(obj)->env;
> - RISCVCPU *cpu = RISCV_CPU(obj);
> -
> - riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH);
> - env->priv_ver = PRIV_VERSION_1_12_0;
> -
> - /* Enable ISA extensions */
> - cpu->cfg.mmu = true;
> - cpu->cfg.ext_zifencei = true;
> - cpu->cfg.ext_zicsr = true;
> - cpu->cfg.pmp = true;
> - cpu->cfg.ext_zicbom = true;
> - cpu->cfg.cbom_blocksize = 64;
> - cpu->cfg.cboz_blocksize = 64;
> - cpu->cfg.ext_zicboz = true;
> - cpu->cfg.ext_smaia = true;
> - cpu->cfg.ext_ssaia = true;
> - cpu->cfg.ext_sscofpmf = true;
> - cpu->cfg.ext_sstc = true;
> - cpu->cfg.ext_svinval = true;
> - cpu->cfg.ext_svnapot = true;
> - cpu->cfg.ext_svpbmt = true;
> - cpu->cfg.ext_smstateen = true;
> - cpu->cfg.ext_zba = true;
> - cpu->cfg.ext_zbb = true;
> - cpu->cfg.ext_zbc = true;
> - cpu->cfg.ext_zbs = true;
> - cpu->cfg.ext_XVentanaCondOps = true;
> -
> - cpu->cfg.mvendorid = VEYRON_V1_MVENDORID;
> - cpu->cfg.marchid = VEYRON_V1_MARCHID;
> - cpu->cfg.mimpid = VEYRON_V1_MIMPID;
> -
> -#ifndef CONFIG_USER_ONLY
> - set_satp_mode_max_supported(cpu, VM_1_10_SV48);
> -#endif
> -}
>
> static void rv64_xiangshan_nanhu_cpu_init(Object *obj)
> {
> @@ -3211,7 +3172,41 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> .cfg.max_satp_mode = VM_1_10_SV57,
> ),
>
> - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1_cpu_init),
> + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_VEYRON_V1, TYPE_RISCV_VENDOR_CPU,
> + .misa_mxl_max = MXL_RV64,
> + .misa_ext = RVG | RVC | RVS | RVU | RVH,
> + .priv_spec = PRIV_VERSION_1_12_0,
> +
> + /* ISA extensions */
> + .cfg.mmu = true,
> + .cfg.ext_zifencei = true,
> + .cfg.ext_zicsr = true,
> + .cfg.pmp = true,
> + .cfg.ext_zicbom = true,
> + .cfg.cbom_blocksize = 64,
> + .cfg.cboz_blocksize = 64,
> + .cfg.ext_zicboz = true,
> + .cfg.ext_smaia = true,
> + .cfg.ext_ssaia = true,
> + .cfg.ext_sscofpmf = true,
> + .cfg.ext_sstc = true,
> + .cfg.ext_svinval = true,
> + .cfg.ext_svnapot = true,
> + .cfg.ext_svpbmt = true,
> + .cfg.ext_smstateen = true,
> + .cfg.ext_zba = true,
> + .cfg.ext_zbb = true,
> + .cfg.ext_zbc = true,
> + .cfg.ext_zbs = true,
> + .cfg.ext_XVentanaCondOps = true,
> +
> + .cfg.mvendorid = VEYRON_V1_MVENDORID,
> + .cfg.marchid = VEYRON_V1_MARCHID,
> + .cfg.mimpid = VEYRON_V1_MIMPID,
> +
> + .cfg.max_satp_mode = VM_1_10_SV48,
> + ),
> +
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU,
> MXL_RV64, rv64_xiangshan_nanhu_cpu_init),
> #ifdef CONFIG_TCG
> --
> 2.49.0
>
next prev parent reply other threads:[~2025-04-24 0:46 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-06 7:02 [PATCH 10.1 v3 00/27] target/riscv: SATP mode and CPU definition overhaul Paolo Bonzini
2025-04-06 7:02 ` [PATCH 01/27] hw/riscv: acpi: only create RHCT MMU entry for supported types Paolo Bonzini
2025-04-06 7:02 ` [PATCH 02/27] target/riscv: assert argument to set_satp_mode_max_supported is valid Paolo Bonzini
2025-04-06 7:02 ` [PATCH 03/27] target/riscv: cpu: store max SATP mode as a single integer Paolo Bonzini
2025-04-06 7:02 ` [PATCH 04/27] target/riscv: update max_satp_mode based on QOM properties Paolo Bonzini
2025-04-06 7:02 ` [PATCH 05/27] target/riscv: remove supported from RISCVSATPMap Paolo Bonzini
2025-04-06 7:02 ` [PATCH 06/27] target/riscv: move satp_mode.{map, init} out of CPUConfig Paolo Bonzini via
2025-04-06 7:02 ` [PATCH 07/27] target/riscv: introduce RISCVCPUDef Paolo Bonzini
2025-04-06 23:21 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 08/27] target/riscv: store RISCVCPUDef struct directly in the class Paolo Bonzini
2025-04-24 13:52 ` Daniel Henrique Barboza
2025-04-24 14:04 ` Philippe Mathieu-Daudé
2025-04-24 14:21 ` Daniel Henrique Barboza
2025-04-06 7:02 ` [PATCH 09/27] target/riscv: merge riscv_cpu_class_init with the class_base function Paolo Bonzini
2025-04-06 7:02 ` [PATCH 10/27] target/riscv: move RISCVCPUConfig fields to a header file Paolo Bonzini
2025-04-06 7:02 ` [PATCH 11/27] target/riscv: include default value in cpu_cfg_fields.h.inc Paolo Bonzini
2025-04-09 4:53 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 12/27] target/riscv: do not make RISCVCPUConfig fields conditional Paolo Bonzini
2025-04-09 5:12 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 13/27] target/riscv: add more RISCVCPUDef fields Paolo Bonzini
2025-04-22 4:47 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 14/27] target/riscv: convert abstract CPU classes to RISCVCPUDef Paolo Bonzini
2025-04-24 0:50 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 15/27] target/riscv: convert profile CPU models " Paolo Bonzini
2025-04-24 0:11 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 16/27] target/riscv: convert bare " Paolo Bonzini
2025-04-24 0:12 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 17/27] target/riscv: convert dynamic " Paolo Bonzini
2025-04-24 0:15 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 18/27] target/riscv: convert SiFive E " Paolo Bonzini
2025-04-24 0:22 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 19/27] target/riscv: convert ibex " Paolo Bonzini
2025-04-24 0:23 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 20/27] target/riscv: convert SiFive U " Paolo Bonzini
2025-04-24 0:25 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 21/27] target/riscv: th: make CSR insertion test a bit more intuitive Paolo Bonzini
2025-04-24 0:32 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 22/27] target/riscv: generalize custom CSR functionality Paolo Bonzini
2025-04-24 0:36 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 23/27] target/riscv: convert TT C906 to RISCVCPUDef Paolo Bonzini
2025-04-24 0:37 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 24/27] target/riscv: convert TT Ascalon " Paolo Bonzini
2025-04-24 0:38 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 25/27] target/riscv: convert Ventana V1 " Paolo Bonzini
2025-04-24 0:45 ` Alistair Francis [this message]
2025-04-06 7:02 ` [PATCH 26/27] target/riscv: convert Xiangshan Nanhu " Paolo Bonzini
2025-04-24 0:47 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 27/27] target/riscv: remove .instance_post_init Paolo Bonzini
2025-04-24 0:48 ` Alistair Francis
2025-04-24 1:26 ` [PATCH 10.1 v3 00/27] target/riscv: SATP mode and CPU definition overhaul Alistair Francis
2025-04-24 14:39 ` Paolo Bonzini
2025-04-25 10:55 ` Paolo Bonzini
2025-04-25 11:02 ` Philippe Mathieu-Daudé
2025-04-25 11:03 ` Paolo Bonzini
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