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Wed, 23 Apr 2025 17:45:41 -0700 (PDT) MIME-Version: 1.0 References: <20250406070254.274797-1-pbonzini@redhat.com> <20250406070254.274797-26-pbonzini@redhat.com> In-Reply-To: <20250406070254.274797-26-pbonzini@redhat.com> From: Alistair Francis Date: Thu, 24 Apr 2025 10:45:15 +1000 X-Gm-Features: ATxdqUFweJhmzz_PAXJGwBN4MwhXcgw4ykmgW8xuj00XThOFnLajGiOHmT06knI Message-ID: Subject: Re: [PATCH 25/27] target/riscv: convert Ventana V1 to RISCVCPUDef To: Paolo Bonzini Cc: qemu-devel@nongnu.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::a36; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa36.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Sun, Apr 6, 2025 at 5:04=E2=80=AFPM Paolo Bonzini = wrote: > > Signed-off-by: Paolo Bonzini Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 75 ++++++++++++++++++++++------------------------ > 1 file changed, 35 insertions(+), 40 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 616d89be17e..4e4d8ddf5a2 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -500,45 +500,6 @@ static void riscv_register_custom_csrs(RISCVCPU *cpu= , const RISCVCSR *csr_list) > #endif > > #if defined(TARGET_RISCV64) > -static void rv64_veyron_v1_cpu_init(Object *obj) > -{ > - CPURISCVState *env =3D &RISCV_CPU(obj)->env; > - RISCVCPU *cpu =3D RISCV_CPU(obj); > - > - riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH); > - env->priv_ver =3D PRIV_VERSION_1_12_0; > - > - /* Enable ISA extensions */ > - cpu->cfg.mmu =3D true; > - cpu->cfg.ext_zifencei =3D true; > - cpu->cfg.ext_zicsr =3D true; > - cpu->cfg.pmp =3D true; > - cpu->cfg.ext_zicbom =3D true; > - cpu->cfg.cbom_blocksize =3D 64; > - cpu->cfg.cboz_blocksize =3D 64; > - cpu->cfg.ext_zicboz =3D true; > - cpu->cfg.ext_smaia =3D true; > - cpu->cfg.ext_ssaia =3D true; > - cpu->cfg.ext_sscofpmf =3D true; > - cpu->cfg.ext_sstc =3D true; > - cpu->cfg.ext_svinval =3D true; > - cpu->cfg.ext_svnapot =3D true; > - cpu->cfg.ext_svpbmt =3D true; > - cpu->cfg.ext_smstateen =3D true; > - cpu->cfg.ext_zba =3D true; > - cpu->cfg.ext_zbb =3D true; > - cpu->cfg.ext_zbc =3D true; > - cpu->cfg.ext_zbs =3D true; > - cpu->cfg.ext_XVentanaCondOps =3D true; > - > - cpu->cfg.mvendorid =3D VEYRON_V1_MVENDORID; > - cpu->cfg.marchid =3D VEYRON_V1_MARCHID; > - cpu->cfg.mimpid =3D VEYRON_V1_MIMPID; > - > -#ifndef CONFIG_USER_ONLY > - set_satp_mode_max_supported(cpu, VM_1_10_SV48); > -#endif > -} > > static void rv64_xiangshan_nanhu_cpu_init(Object *obj) > { > @@ -3211,7 +3172,41 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { > .cfg.max_satp_mode =3D VM_1_10_SV57, > ), > > - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_= v1_cpu_init), > + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_VEYRON_V1, TYPE_RISCV_VENDOR_CPU, > + .misa_mxl_max =3D MXL_RV64, > + .misa_ext =3D RVG | RVC | RVS | RVU | RVH, > + .priv_spec =3D PRIV_VERSION_1_12_0, > + > + /* ISA extensions */ > + .cfg.mmu =3D true, > + .cfg.ext_zifencei =3D true, > + .cfg.ext_zicsr =3D true, > + .cfg.pmp =3D true, > + .cfg.ext_zicbom =3D true, > + .cfg.cbom_blocksize =3D 64, > + .cfg.cboz_blocksize =3D 64, > + .cfg.ext_zicboz =3D true, > + .cfg.ext_smaia =3D true, > + .cfg.ext_ssaia =3D true, > + .cfg.ext_sscofpmf =3D true, > + .cfg.ext_sstc =3D true, > + .cfg.ext_svinval =3D true, > + .cfg.ext_svnapot =3D true, > + .cfg.ext_svpbmt =3D true, > + .cfg.ext_smstateen =3D true, > + .cfg.ext_zba =3D true, > + .cfg.ext_zbb =3D true, > + .cfg.ext_zbc =3D true, > + .cfg.ext_zbs =3D true, > + .cfg.ext_XVentanaCondOps =3D true, > + > + .cfg.mvendorid =3D VEYRON_V1_MVENDORID, > + .cfg.marchid =3D VEYRON_V1_MARCHID, > + .cfg.mimpid =3D VEYRON_V1_MIMPID, > + > + .cfg.max_satp_mode =3D VM_1_10_SV48, > + ), > + > DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, > MXL_RV64, rv64_xiangsha= n_nanhu_cpu_init), > #ifdef CONFIG_TCG > -- > 2.49.0 >