From: Alistair Francis <alistair23@gmail.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <alistair.francis@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH v2 7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
Date: Wed, 3 Nov 2021 16:00:19 +1000 [thread overview]
Message-ID: <CAKmqyKNnQ9G8K7b4t32JhBdyEisn2=++g1R2kxssYMTSu08iSg@mail.gmail.com> (raw)
In-Reply-To: <20211030135513.18517-8-bin.meng@windriver.com>
On Sun, Oct 31, 2021 at 12:02 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> This is now used by RISC-V as well. Update the comments.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
>
> ---
>
> (no changes since v1)
>
> include/hw/core/tcg-cpu-ops.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
> index 6cbe17f2e6..532c148a80 100644
> --- a/include/hw/core/tcg-cpu-ops.h
> +++ b/include/hw/core/tcg-cpu-ops.h
> @@ -92,6 +92,7 @@ struct TCGCPUOps {
> /**
> * @debug_check_watchpoint: return true if the architectural
> * watchpoint whose address has matched should really fire, used by ARM
> + * and RISC-V
> */
> bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
>
> --
> 2.25.1
>
>
prev parent reply other threads:[~2021-11-03 6:02 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-30 13:55 [PATCH v2 0/7] target/riscv: Initial support for native debug feature via M-mode CSRs Bin Meng
2021-10-30 13:55 ` [PATCH v2 1/7] target/riscv: Add initial support for native debug Bin Meng
2021-10-30 13:55 ` [PATCH v2 2/7] target/riscv: machine: Add debug state description Bin Meng
2021-11-17 0:50 ` Alistair Francis
2021-10-30 13:55 ` [PATCH v2 3/7] target/riscv: debug: Implement debug related TCGCPUOps Bin Meng
2021-11-17 0:54 ` Alistair Francis
2021-10-30 13:55 ` [PATCH v2 4/7] target/riscv: cpu: Add a config option for native debug Bin Meng
2021-11-03 5:59 ` Alistair Francis
2021-10-30 13:55 ` [PATCH v2 5/7] target/riscv: csr: Hook debug CSR read/write Bin Meng
2021-11-17 0:56 ` Alistair Francis
2021-10-30 13:55 ` [PATCH v2 6/7] target/riscv: cpu: Enable native debug feature on virt and sifive_u CPUs Bin Meng
2021-11-17 0:57 ` Alistair Francis
2021-11-17 9:51 ` Bin Meng
2021-10-30 13:55 ` [PATCH v2 7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() Bin Meng
2021-11-03 6:00 ` Alistair Francis [this message]
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