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From: Alistair Francis <alistair23@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
	alistair.francis@wdc.com,  dbarboza@ventanamicro.com
Subject: Re: [PATCH 2/7] target/riscv: Pass ra to riscv_csrrw_do64
Date: Tue, 29 Apr 2025 08:34:13 +1000	[thread overview]
Message-ID: <CAKmqyKNr0-su0dOvs+OQPMGsoyh61d4e4Kdb=Wayakh-FCz6nA@mail.gmail.com> (raw)
In-Reply-To: <20250425152311.804338-3-richard.henderson@linaro.org>

On Sat, Apr 26, 2025 at 1:25 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/csr.c | 15 +++++++--------
>  1 file changed, 7 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 6f1f69eba6..e9c2f95b6e 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -5516,7 +5516,8 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
>  static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
>                                         target_ulong *ret_value,
>                                         target_ulong new_value,
> -                                       target_ulong write_mask)
> +                                       target_ulong write_mask,
> +                                       uintptr_t ra)
>  {
>      RISCVException ret;
>      target_ulong old_value = 0;
> @@ -5546,7 +5547,7 @@ static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
>      if (write_mask) {
>          new_value = (old_value & ~write_mask) | (new_value & write_mask);
>          if (csr_ops[csrno].write) {
> -            ret = csr_ops[csrno].write(env, csrno, new_value, 0);
> +            ret = csr_ops[csrno].write(env, csrno, new_value, ra);
>              if (ret != RISCV_EXCP_NONE) {
>                  return ret;
>              }
> @@ -5569,7 +5570,7 @@ RISCVException riscv_csrr(CPURISCVState *env, int csrno,
>          return ret;
>      }
>
> -    return riscv_csrrw_do64(env, csrno, ret_value, 0, 0);
> +    return riscv_csrrw_do64(env, csrno, ret_value, 0, 0, 0);
>  }
>
>  RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
> @@ -5581,7 +5582,7 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
>          return ret;
>      }
>
> -    return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask);
> +    return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask, 0);
>  }
>
>  static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
> @@ -5647,9 +5648,7 @@ RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
>       * accesses
>       */
>      target_ulong old_value;
> -    ret = riscv_csrrw_do64(env, csrno, &old_value,
> -                           (target_ulong)0,
> -                           (target_ulong)0);
> +    ret = riscv_csrrw_do64(env, csrno, &old_value, 0, 0, 0);
>      if (ret == RISCV_EXCP_NONE && ret_value) {
>          *ret_value = int128_make64(old_value);
>      }
> @@ -5681,7 +5680,7 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
>      target_ulong old_value;
>      ret = riscv_csrrw_do64(env, csrno, &old_value,
>                             int128_getlo(new_value),
> -                           int128_getlo(write_mask));
> +                           int128_getlo(write_mask), 0);
>      if (ret == RISCV_EXCP_NONE && ret_value) {
>          *ret_value = int128_make64(old_value);
>      }
> --
> 2.43.0
>
>


  parent reply	other threads:[~2025-04-28 22:35 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-25 15:23 [PATCH 0/7] target/riscv: Fix write_misa vs aligned next_pc Richard Henderson
2025-04-25 15:23 ` [PATCH 1/7] target/riscv: Pass ra to riscv_csr_write_fn Richard Henderson
2025-04-25 22:28   ` Philippe Mathieu-Daudé
2025-04-28 22:33   ` Alistair Francis
2025-04-25 15:23 ` [PATCH 2/7] target/riscv: Pass ra to riscv_csrrw_do64 Richard Henderson
2025-04-25 22:29   ` Philippe Mathieu-Daudé
2025-04-28 22:34   ` Alistair Francis [this message]
2025-04-25 15:23 ` [PATCH 3/7] target/riscv: Pass ra to riscv_csrrw_do128 Richard Henderson
2025-04-25 22:29   ` Philippe Mathieu-Daudé
2025-04-28 22:34   ` Alistair Francis
2025-04-25 15:23 ` [PATCH 4/7] target/riscv: Pass ra to riscv_csrrw Richard Henderson
2025-04-25 22:31   ` Philippe Mathieu-Daudé
2025-04-28 22:36   ` Alistair Francis
2025-04-25 15:23 ` [PATCH 5/7] target/riscv: Pass ra to riscv_csrrw_i128 Richard Henderson
2025-04-25 22:32   ` Philippe Mathieu-Daudé
2025-04-28 22:37   ` Alistair Francis
2025-04-25 15:23 ` [PATCH 6/7] target/riscv: Move insn_len to internals.h Richard Henderson
2025-04-25 22:33   ` Philippe Mathieu-Daudé
2025-04-28 22:37   ` Alistair Francis
2025-04-25 15:23 ` [PATCH 7/7] target/riscv: Fix write_misa vs aligned next_pc Richard Henderson
2025-04-25 22:33   ` Philippe Mathieu-Daudé
2025-04-28 22:39   ` Alistair Francis
2025-04-29 14:33   ` Richard Henderson
2025-04-30 22:44     ` Alistair Francis
2025-05-14 21:33   ` Daniel Henrique Barboza
2025-05-15  8:10     ` Richard Henderson
2025-04-26  8:25 ` [PATCH 0/7] " Daniel Henrique Barboza
2025-04-28 22:46 ` Alistair Francis

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