From: Alistair Francis <alistair23@gmail.com>
To: Bin Meng <bmeng@tinylab.org>
Cc: Alistair Francis <Alistair.Francis@wdc.com>,
qemu-devel@nongnu.org, Bin Meng <bin.meng@windriver.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
qemu-riscv@nongnu.org
Subject: Re: [PATCH 08/15] hw/intc: sifive_plic: Update "num-sources" property default value
Date: Wed, 7 Dec 2022 14:28:42 +1000 [thread overview]
Message-ID: <CAKmqyKNrFL19uEhPWYwnmH82d-2ZBdpcBounU2Eo2xz9dbjvqQ@mail.gmail.com> (raw)
In-Reply-To: <20221201140811.142123-8-bmeng@tinylab.org>
On Fri, Dec 2, 2022 at 12:12 AM Bin Meng <bmeng@tinylab.org> wrote:
>
> At present the default value of "num-sources" property is zero,
> which does not make a lot of sense, as in sifive_plic_realize()
> we see s->bitfield_words is calculated by:
>
> s->bitfield_words = (s->num_sources + 31) >> 5;
>
> if the we don't configure "num-sources" property its default value
> zero makes s->bitfield_words zero too, which isn't true because
> interrupt source 0 still occupies one word.
>
> Let's change the default value to 1 meaning that only interrupt
> source 0 is supported by default and a sanity check in realize().
>
> While we are here, add a comment to describe the exact meaning of
> this property that the number should include interrupt source 0.
> A wrong multi-line comment format is corrected too.
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> ---
>
> hw/intc/sifive_plic.c | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
> index 5fd9a53569..2bd292410d 100644
> --- a/hw/intc/sifive_plic.c
> +++ b/hw/intc/sifive_plic.c
> @@ -363,6 +363,11 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
>
> parse_hart_config(s);
>
> + if (!s->num_sources) {
> + error_report("plic: invalid number of interrupt sources");
We should propagate the error up via errp instead
Otherwise:
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> + exit(1);
> + }
> +
> s->bitfield_words = (s->num_sources + 31) >> 5;
> s->num_enables = s->bitfield_words * s->num_addrs;
> s->source_priority = g_new0(uint32_t, s->num_sources);
> @@ -379,7 +384,8 @@ static void sifive_plic_realize(DeviceState *dev, Error **errp)
> s->m_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts);
> qdev_init_gpio_out(dev, s->m_external_irqs, s->num_harts);
>
> - /* We can't allow the supervisor to control SEIP as this would allow the
> + /*
> + * We can't allow the supervisor to control SEIP as this would allow the
> * supervisor to clear a pending external interrupt which will result in
> * lost a interrupt in the case a PLIC is attached. The SEIP bit must be
> * hardware controlled when a PLIC is attached.
> @@ -419,7 +425,8 @@ static const VMStateDescription vmstate_sifive_plic = {
> static Property sifive_plic_properties[] = {
> DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
> DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0),
> - DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0),
> + /* number of interrupt sources including interrupt source 0 */
> + DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 1),
> DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
> DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
> DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
> --
> 2.34.1
>
>
next prev parent reply other threads:[~2022-12-07 4:29 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-01 14:07 [PATCH 01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Bin Meng
2022-12-01 14:07 ` [PATCH 02/15] hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers Bin Meng
2022-12-04 22:23 ` Alistair Francis
2022-12-01 14:07 ` [PATCH 03/15] hw/riscv: Fix opentitan dependency to SIFIVE_PLIC Bin Meng
2022-12-01 23:36 ` Wilfred Mallawa
2022-12-04 22:23 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 04/15] hw/riscv: Sort machines Kconfig options in alphabetical order Bin Meng
2022-12-04 22:24 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 05/15] hw/riscv: spike: Remove misleading comments Bin Meng
2022-12-01 23:39 ` Wilfred Mallawa
2022-12-04 22:25 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 06/15] hw/intc: sifive_plic: Drop PLICMode_H Bin Meng
2022-12-01 23:57 ` Wilfred Mallawa
2022-12-04 22:25 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 07/15] hw/intc: sifive_plic: Improve robustness of the PLIC config parser Bin Meng
2022-12-07 4:21 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 08/15] hw/intc: sifive_plic: Update "num-sources" property default value Bin Meng
2022-12-07 4:28 ` Alistair Francis [this message]
2022-12-01 14:08 ` [PATCH 09/15] hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC Bin Meng
2022-12-02 0:03 ` Wilfred Mallawa
2022-12-07 4:30 ` Alistair Francis
2022-12-07 8:29 ` Conor Dooley
2022-12-01 14:08 ` [PATCH 10/15] hw/riscv: sifive_e: " Bin Meng
2022-12-02 0:05 ` Wilfred Mallawa
2022-12-07 4:31 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 11/15] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" Bin Meng
2022-12-02 0:06 ` Wilfred Mallawa
2022-12-07 4:33 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 12/15] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb Bin Meng
2022-12-07 4:35 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 13/15] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 Bin Meng
2022-12-07 4:36 ` Alistair Francis
2022-12-01 14:08 ` [PATCH 14/15] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization Bin Meng
2022-12-02 0:11 ` Wilfred Mallawa
2022-12-07 4:37 ` Alistair Francis
2022-12-07 10:11 ` Bin Meng
2022-12-01 14:08 ` [PATCH 15/15] hw/intc: sifive_plic: Fix the pending register range check Bin Meng
2022-12-02 0:27 ` Wilfred Mallawa
2022-12-05 8:21 ` Bin Meng
2022-12-05 22:05 ` Wilfred Mallawa
2022-12-07 5:08 ` Alistair Francis
2022-12-04 22:21 ` [PATCH 01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC Alistair Francis
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