* [Qemu-devel] [PATCH-for-4.2 0/2] target/riscv/pmp: Convert to trace events @ 2019-07-23 12:08 Philippe Mathieu-Daudé 2019-07-23 12:08 ` [Qemu-devel] [PATCH-for-4.2 1/2] target/riscv/pmp: Restrict priviledged PMP to system-mode emulation Philippe Mathieu-Daudé 2019-07-23 12:08 ` [Qemu-devel] [PATCH-for-4.2 2/2] target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events Philippe Mathieu-Daudé 0 siblings, 2 replies; 5+ messages in thread From: Philippe Mathieu-Daudé @ 2019-07-23 12:08 UTC (permalink / raw) To: qemu-devel Cc: qemu-riscv, Sagar Karandikar, Bastian Koppelmann, Palmer Dabbelt, KONRAD Frederic, Alistair Francis, Philippe Mathieu-Daudé Trivial convertion, suggested on https://lists.gnu.org/archive/html/qemu-devel/2019-07/msg04728.html Philippe Mathieu-Daudé (2): target/riscv/pmp: Restrict priviledged PMP to system-mode emulation target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events target/riscv/Makefile.objs | 3 ++- target/riscv/pmp.c | 35 ++++++++++------------------------- target/riscv/trace-events | 6 ++++++ 3 files changed, 18 insertions(+), 26 deletions(-) -- 2.20.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [Qemu-devel] [PATCH-for-4.2 1/2] target/riscv/pmp: Restrict priviledged PMP to system-mode emulation 2019-07-23 12:08 [Qemu-devel] [PATCH-for-4.2 0/2] target/riscv/pmp: Convert to trace events Philippe Mathieu-Daudé @ 2019-07-23 12:08 ` Philippe Mathieu-Daudé 2019-07-23 18:05 ` Alistair Francis 2019-07-23 12:08 ` [Qemu-devel] [PATCH-for-4.2 2/2] target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events Philippe Mathieu-Daudé 1 sibling, 1 reply; 5+ messages in thread From: Philippe Mathieu-Daudé @ 2019-07-23 12:08 UTC (permalink / raw) To: qemu-devel Cc: qemu-riscv, Sagar Karandikar, Bastian Koppelmann, Palmer Dabbelt, KONRAD Frederic, Alistair Francis, Philippe Mathieu-Daudé The RISC-V Physical Memory Protection is restricted to privileged modes. Restrict its compilation to QEMU system builds. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> --- target/riscv/Makefile.objs | 3 ++- target/riscv/pmp.c | 4 ---- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index b1c79bc1d1..b754e4bf32 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -1,4 +1,5 @@ -obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o gdbstub.o pmp.o +obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o gdbstub.o +obj-$(CONFIG_SOFTMMU) += pmp.o DECODETREE = $(SRC_PATH)/scripts/decodetree.py diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 958c7502a0..d836288cb4 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -28,8 +28,6 @@ #include "qapi/error.h" #include "cpu.h" -#ifndef CONFIG_USER_ONLY - #define RISCV_DEBUG_PMP 0 #define PMP_DEBUG(fmt, ...) \ do { \ @@ -382,5 +380,3 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index) return 0; } } - -#endif -- 2.20.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [Qemu-devel] [PATCH-for-4.2 1/2] target/riscv/pmp: Restrict priviledged PMP to system-mode emulation 2019-07-23 12:08 ` [Qemu-devel] [PATCH-for-4.2 1/2] target/riscv/pmp: Restrict priviledged PMP to system-mode emulation Philippe Mathieu-Daudé @ 2019-07-23 18:05 ` Alistair Francis 0 siblings, 0 replies; 5+ messages in thread From: Alistair Francis @ 2019-07-23 18:05 UTC (permalink / raw) To: Philippe Mathieu-Daudé Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann, Palmer Dabbelt, qemu-devel@nongnu.org Developers, KONRAD Frederic, Alistair Francis On Tue, Jul 23, 2019 at 5:08 AM Philippe Mathieu-Daudé <philmd@redhat.com> wrote: > > The RISC-V Physical Memory Protection is restricted to privileged > modes. Restrict its compilation to QEMU system builds. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/Makefile.objs | 3 ++- > target/riscv/pmp.c | 4 ---- > 2 files changed, 2 insertions(+), 5 deletions(-) > > diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs > index b1c79bc1d1..b754e4bf32 100644 > --- a/target/riscv/Makefile.objs > +++ b/target/riscv/Makefile.objs > @@ -1,4 +1,5 @@ > -obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o gdbstub.o pmp.o > +obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o gdbstub.o > +obj-$(CONFIG_SOFTMMU) += pmp.o > > DECODETREE = $(SRC_PATH)/scripts/decodetree.py > > diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c > index 958c7502a0..d836288cb4 100644 > --- a/target/riscv/pmp.c > +++ b/target/riscv/pmp.c > @@ -28,8 +28,6 @@ > #include "qapi/error.h" > #include "cpu.h" > > -#ifndef CONFIG_USER_ONLY > - > #define RISCV_DEBUG_PMP 0 > #define PMP_DEBUG(fmt, ...) \ > do { \ > @@ -382,5 +380,3 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index) > return 0; > } > } > - > -#endif > -- > 2.20.1 > > ^ permalink raw reply [flat|nested] 5+ messages in thread
* [Qemu-devel] [PATCH-for-4.2 2/2] target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events 2019-07-23 12:08 [Qemu-devel] [PATCH-for-4.2 0/2] target/riscv/pmp: Convert to trace events Philippe Mathieu-Daudé 2019-07-23 12:08 ` [Qemu-devel] [PATCH-for-4.2 1/2] target/riscv/pmp: Restrict priviledged PMP to system-mode emulation Philippe Mathieu-Daudé @ 2019-07-23 12:08 ` Philippe Mathieu-Daudé 2019-07-23 18:06 ` Alistair Francis 1 sibling, 1 reply; 5+ messages in thread From: Philippe Mathieu-Daudé @ 2019-07-23 12:08 UTC (permalink / raw) To: qemu-devel Cc: qemu-riscv, Sagar Karandikar, Bastian Koppelmann, Palmer Dabbelt, KONRAD Frederic, Alistair Francis, Philippe Mathieu-Daudé Use the always-compiled trace events, remove the now unused RISCV_DEBUG_PMP definition. Note pmpaddr_csr_read() could previously do out-of-bound accesses passing addr_index >= MAX_RISCV_PMPS. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> --- target/riscv/pmp.c | 31 ++++++++++--------------------- target/riscv/trace-events | 6 ++++++ 2 files changed, 16 insertions(+), 21 deletions(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index d836288cb4..d4f1007109 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -27,14 +27,7 @@ #include "qemu/log.h" #include "qapi/error.h" #include "cpu.h" - -#define RISCV_DEBUG_PMP 0 -#define PMP_DEBUG(fmt, ...) \ - do { \ - if (RISCV_DEBUG_PMP) { \ - qemu_log_mask(LOG_TRACE, "%s: " fmt "\n", __func__, ##__VA_ARGS__);\ - } \ - } while (0) +#include "trace.h" static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index, uint8_t val); @@ -302,8 +295,7 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, int i; uint8_t cfg_val; - PMP_DEBUG("hart " TARGET_FMT_ld ": reg%d, val: 0x" TARGET_FMT_lx, - env->mhartid, reg_index, val); + trace_pmpcfg_csr_write(env->mhartid, reg_index, val); if ((reg_index & 1) && (sizeof(target_ulong) == 8)) { qemu_log_mask(LOG_GUEST_ERROR, @@ -332,9 +324,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index) val = pmp_read_cfg(env, (reg_index * sizeof(target_ulong)) + i); cfg_val |= (val << (i * 8)); } - - PMP_DEBUG("hart " TARGET_FMT_ld ": reg%d, val: 0x" TARGET_FMT_lx, - env->mhartid, reg_index, cfg_val); + trace_pmpcfg_csr_read(env->mhartid, reg_index, cfg_val); return cfg_val; } @@ -346,9 +336,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index) void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, target_ulong val) { - PMP_DEBUG("hart " TARGET_FMT_ld ": addr%d, val: 0x" TARGET_FMT_lx, - env->mhartid, addr_index, val); - + trace_pmpaddr_csr_write(env->mhartid, addr_index, val); if (addr_index < MAX_RISCV_PMPS) { if (!pmp_is_locked(env, addr_index)) { env->pmp_state.pmp[addr_index].addr_reg = val; @@ -369,14 +357,15 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, */ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index) { - PMP_DEBUG("hart " TARGET_FMT_ld ": addr%d, val: 0x" TARGET_FMT_lx, - env->mhartid, addr_index, - env->pmp_state.pmp[addr_index].addr_reg); + target_ulong val = 0; + if (addr_index < MAX_RISCV_PMPS) { - return env->pmp_state.pmp[addr_index].addr_reg; + val = env->pmp_state.pmp[addr_index].addr_reg; + trace_pmpaddr_csr_read(env->mhartid, addr_index, val); } else { qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpaddr read - out of bounds\n"); - return 0; } + + return val; } diff --git a/target/riscv/trace-events b/target/riscv/trace-events index 48af0373df..4b6c652ae9 100644 --- a/target/riscv/trace-events +++ b/target/riscv/trace-events @@ -1,2 +1,8 @@ # target/riscv/cpu_helper.c riscv_trap(uint64_t hartid, bool async, uint64_t cause, uint64_t epc, uint64_t tval, const char *desc) "hart:%"PRId64", async:%d, cause:%"PRId64", epc:0x%"PRIx64", tval:0x%"PRIx64", desc=%s" + +# pmp.c +pmpcfg_csr_read(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": read reg%" PRIu32", val: 0x%" PRIx64 +pmpcfg_csr_write(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": write reg%" PRIu32", val: 0x%" PRIx64 +pmpaddr_csr_read(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": read addr%" PRIu32", val: 0x%" PRIx64 +pmpaddr_csr_write(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": write addr%" PRIu32", val: 0x%" PRIx64 -- 2.20.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [Qemu-devel] [PATCH-for-4.2 2/2] target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events 2019-07-23 12:08 ` [Qemu-devel] [PATCH-for-4.2 2/2] target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events Philippe Mathieu-Daudé @ 2019-07-23 18:06 ` Alistair Francis 0 siblings, 0 replies; 5+ messages in thread From: Alistair Francis @ 2019-07-23 18:06 UTC (permalink / raw) To: Philippe Mathieu-Daudé Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann, Palmer Dabbelt, qemu-devel@nongnu.org Developers, KONRAD Frederic, Alistair Francis On Tue, Jul 23, 2019 at 5:08 AM Philippe Mathieu-Daudé <philmd@redhat.com> wrote: > > Use the always-compiled trace events, remove the now unused > RISCV_DEBUG_PMP definition. > > Note pmpaddr_csr_read() could previously do out-of-bound accesses > passing addr_index >= MAX_RISCV_PMPS. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/pmp.c | 31 ++++++++++--------------------- > target/riscv/trace-events | 6 ++++++ > 2 files changed, 16 insertions(+), 21 deletions(-) > > diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c > index d836288cb4..d4f1007109 100644 > --- a/target/riscv/pmp.c > +++ b/target/riscv/pmp.c > @@ -27,14 +27,7 @@ > #include "qemu/log.h" > #include "qapi/error.h" > #include "cpu.h" > - > -#define RISCV_DEBUG_PMP 0 > -#define PMP_DEBUG(fmt, ...) \ > - do { \ > - if (RISCV_DEBUG_PMP) { \ > - qemu_log_mask(LOG_TRACE, "%s: " fmt "\n", __func__, ##__VA_ARGS__);\ > - } \ > - } while (0) > +#include "trace.h" > > static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index, > uint8_t val); > @@ -302,8 +295,7 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, > int i; > uint8_t cfg_val; > > - PMP_DEBUG("hart " TARGET_FMT_ld ": reg%d, val: 0x" TARGET_FMT_lx, > - env->mhartid, reg_index, val); > + trace_pmpcfg_csr_write(env->mhartid, reg_index, val); > > if ((reg_index & 1) && (sizeof(target_ulong) == 8)) { > qemu_log_mask(LOG_GUEST_ERROR, > @@ -332,9 +324,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index) > val = pmp_read_cfg(env, (reg_index * sizeof(target_ulong)) + i); > cfg_val |= (val << (i * 8)); > } > - > - PMP_DEBUG("hart " TARGET_FMT_ld ": reg%d, val: 0x" TARGET_FMT_lx, > - env->mhartid, reg_index, cfg_val); > + trace_pmpcfg_csr_read(env->mhartid, reg_index, cfg_val); > > return cfg_val; > } > @@ -346,9 +336,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index) > void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, > target_ulong val) > { > - PMP_DEBUG("hart " TARGET_FMT_ld ": addr%d, val: 0x" TARGET_FMT_lx, > - env->mhartid, addr_index, val); > - > + trace_pmpaddr_csr_write(env->mhartid, addr_index, val); > if (addr_index < MAX_RISCV_PMPS) { > if (!pmp_is_locked(env, addr_index)) { > env->pmp_state.pmp[addr_index].addr_reg = val; > @@ -369,14 +357,15 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, > */ > target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index) > { > - PMP_DEBUG("hart " TARGET_FMT_ld ": addr%d, val: 0x" TARGET_FMT_lx, > - env->mhartid, addr_index, > - env->pmp_state.pmp[addr_index].addr_reg); > + target_ulong val = 0; > + > if (addr_index < MAX_RISCV_PMPS) { > - return env->pmp_state.pmp[addr_index].addr_reg; > + val = env->pmp_state.pmp[addr_index].addr_reg; > + trace_pmpaddr_csr_read(env->mhartid, addr_index, val); > } else { > qemu_log_mask(LOG_GUEST_ERROR, > "ignoring pmpaddr read - out of bounds\n"); > - return 0; > } > + > + return val; > } > diff --git a/target/riscv/trace-events b/target/riscv/trace-events > index 48af0373df..4b6c652ae9 100644 > --- a/target/riscv/trace-events > +++ b/target/riscv/trace-events > @@ -1,2 +1,8 @@ > # target/riscv/cpu_helper.c > riscv_trap(uint64_t hartid, bool async, uint64_t cause, uint64_t epc, uint64_t tval, const char *desc) "hart:%"PRId64", async:%d, cause:%"PRId64", epc:0x%"PRIx64", tval:0x%"PRIx64", desc=%s" > + > +# pmp.c > +pmpcfg_csr_read(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": read reg%" PRIu32", val: 0x%" PRIx64 > +pmpcfg_csr_write(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": write reg%" PRIu32", val: 0x%" PRIx64 > +pmpaddr_csr_read(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": read addr%" PRIu32", val: 0x%" PRIx64 > +pmpaddr_csr_write(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": write addr%" PRIu32", val: 0x%" PRIx64 > -- > 2.20.1 > > ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2019-07-23 18:10 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2019-07-23 12:08 [Qemu-devel] [PATCH-for-4.2 0/2] target/riscv/pmp: Convert to trace events Philippe Mathieu-Daudé 2019-07-23 12:08 ` [Qemu-devel] [PATCH-for-4.2 1/2] target/riscv/pmp: Restrict priviledged PMP to system-mode emulation Philippe Mathieu-Daudé 2019-07-23 18:05 ` Alistair Francis 2019-07-23 12:08 ` [Qemu-devel] [PATCH-for-4.2 2/2] target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events Philippe Mathieu-Daudé 2019-07-23 18:06 ` Alistair Francis
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