From: Alistair Francis <alistair23@gmail.com>
To: Ethan Chen <ethan84@andestech.com>
Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org,
pbonzini@redhat.com, palmer@dabbelt.com,
alistair.francis@wdc.com, bmeng.cn@gmail.com,
liwei1518@gmail.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, peterx@redhat.com,
david@redhat.com, philmd@linaro.org, qemu-riscv@nongnu.org
Subject: Re: [PATCH v10 5/8] hw/misc/riscv_iopmp_txn_info: Add struct for transaction infomation
Date: Fri, 28 Feb 2025 11:57:25 +1000 [thread overview]
Message-ID: <CAKmqyKNu3NDom_8Yp1fcX+douovDCPD_VQejxOr43M3cp49-dA@mail.gmail.com> (raw)
In-Reply-To: <20250122084630.3965707-1-ethan84@andestech.com>
On Wed, Jan 22, 2025 at 6:49 PM Ethan Chen via <qemu-devel@nongnu.org> wrote:
>
> The entire valid transaction must fit within a single IOPMP entry.
> However, during IOMMU translation, the transaction size is not
> available. This structure defines the transaction information required
> by the IOPMP.
>
> Signed-off-by: Ethan Chen <ethan84@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> include/hw/misc/riscv_iopmp_txn_info.h | 38 ++++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
> create mode 100644 include/hw/misc/riscv_iopmp_txn_info.h
>
> diff --git a/include/hw/misc/riscv_iopmp_txn_info.h b/include/hw/misc/riscv_iopmp_txn_info.h
> new file mode 100644
> index 0000000000..98bd26b68b
> --- /dev/null
> +++ b/include/hw/misc/riscv_iopmp_txn_info.h
> @@ -0,0 +1,38 @@
> +/*
> + * QEMU RISC-V IOPMP transaction information
> + *
> + * The transaction information structure provides the complete transaction
> + * length to the IOPMP device
> + *
> + * Copyright (c) 2023-2025 Andes Tech. Corp.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef RISCV_IOPMP_TXN_INFO_H
> +#define RISCV_IOPMP_TXN_INFO_H
> +
> +typedef struct {
> + /* The id of requestor */
> + uint32_t rrid:16;
> + /* The start address of transaction */
> + uint64_t start_addr;
> + /* The end address of transaction */
> + uint64_t end_addr;
> + /* The stage of cascading IOPMP */
> + uint32_t stage;
> +} riscv_iopmp_txn_info;
> +
> +#endif
> --
> 2.34.1
>
>
next prev parent reply other threads:[~2025-02-28 1:58 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-22 8:36 [PATCH v10 0/8] Support RISC-V IOPMP Ethan Chen via
2025-01-22 8:36 ` [PATCH v10 1/8] hw/core: Add config stream Ethan Chen via
2025-01-22 8:36 ` [PATCH v10 2/8] memory: Introduce memory region fetch operation Ethan Chen via
2025-02-28 1:19 ` Alistair Francis
2025-01-22 8:36 ` [PATCH v10 3/8] system/physmem: Support IOMMU granularity smaller than TARGET_PAGE size Ethan Chen via
2025-01-22 8:36 ` [PATCH v10 4/8] target/riscv: Add support for IOPMP Ethan Chen via
2025-01-22 8:46 ` [PATCH v10 5/8] hw/misc/riscv_iopmp_txn_info: Add struct for transaction infomation Ethan Chen via
2025-02-28 1:57 ` Alistair Francis [this message]
2025-02-28 5:59 ` Alistair Francis
2025-01-22 8:46 ` [PATCH v10 6/8] hw/misc/riscv_iopmp: Add RISC-V IOPMP device Ethan Chen via
2025-02-28 5:51 ` Alistair Francis
2025-01-22 8:47 ` [PATCH v10 7/8] hw/misc/riscv_iopmp_dispatcher: Device for redirect IOPMP transaction infomation Ethan Chen via
2025-02-28 6:00 ` Alistair Francis
2025-01-22 8:47 ` [PATCH v10 8/8] hw/riscv/virt: Add IOPMP support Ethan Chen via
2025-02-28 6:02 ` Alistair Francis
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