From: Alistair Francis <alistair23@gmail.com>
To: Frank Chang <frank.chang@sifive.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Bin Meng <bin.meng@windriver.com>,
Richard Henderson <richard.henderson@linaro.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <alistair.francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v10 04/77] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty
Date: Mon, 29 Nov 2021 13:16:44 +1000 [thread overview]
Message-ID: <CAKmqyKNuR5NKn3v6hzXu+4=CwsS46jQg10efqtOfrGuY773+xg@mail.gmail.com> (raw)
In-Reply-To: <20211129030340.429689-5-frank.chang@sifive.com>
On Mon, Nov 29, 2021 at 1:07 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 9b5bd5d7b49..bb500afdeb5 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -502,6 +502,7 @@ static RISCVException read_mhartid(CPURISCVState *env, int csrno,
> static uint64_t add_status_sd(RISCVMXL xl, uint64_t status)
> {
> if ((status & MSTATUS_FS) == MSTATUS_FS ||
> + (status & MSTATUS_VS) == MSTATUS_VS ||
> (status & MSTATUS_XS) == MSTATUS_XS) {
> switch (xl) {
> case MXL_RV32:
> --
> 2.25.1
>
>
next prev parent reply other threads:[~2021-11-29 3:50 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-29 3:02 [PATCH v10 00/77] support vector extension v1.0 frank.chang
2021-11-29 3:02 ` [PATCH v10 01/77] target/riscv: drop vector 0.7.1 and add 1.0 support frank.chang
2021-11-29 3:02 ` [PATCH v10 02/77] target/riscv: Use FIELD_EX32() to extract wd field frank.chang
2021-11-29 3:02 ` [PATCH v10 03/77] target/riscv: rvv-1.0: add mstatus VS field frank.chang
2021-11-29 3:02 ` [PATCH v10 04/77] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty frank.chang
2021-11-29 3:16 ` Alistair Francis [this message]
2021-11-29 3:02 ` [PATCH v10 05/77] target/riscv: rvv-1.0: add sstatus VS field frank.chang
2021-11-29 3:02 ` [PATCH v10 06/77] target/riscv: rvv-1.0: introduce writable misa.v field frank.chang
2021-11-29 3:02 ` [PATCH v10 07/77] target/riscv: rvv-1.0: add translation-time vector context status frank.chang
2021-11-29 3:02 ` [PATCH v10 08/77] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers frank.chang
2021-11-29 3:02 ` [PATCH v10 09/77] target/riscv: rvv-1.0: add vcsr register frank.chang
2021-11-29 3:02 ` [PATCH v10 10/77] target/riscv: rvv-1.0: add vlenb register frank.chang
2021-11-29 3:02 ` [PATCH v10 11/77] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers frank.chang
2021-11-29 3:02 ` [PATCH v10 12/77] target/riscv: rvv-1.0: remove MLEN calculations frank.chang
2021-11-29 3:02 ` [PATCH v10 13/77] target/riscv: rvv-1.0: add fractional LMUL frank.chang
2021-11-29 3:02 ` [PATCH v10 14/77] target/riscv: rvv-1.0: add VMA and VTA frank.chang
2021-11-29 3:02 ` [PATCH v10 15/77] target/riscv: rvv-1.0: update check functions frank.chang
2021-11-29 3:02 ` [PATCH v10 16/77] target/riscv: introduce more imm value modes in translator functions frank.chang
2021-11-29 3:02 ` [PATCH v10 17/77] target/riscv: rvv:1.0: add translation-time nan-box helper function frank.chang
2021-11-29 3:02 ` [PATCH v10 18/77] target/riscv: rvv-1.0: remove amo operations instructions frank.chang
2021-11-29 3:02 ` [PATCH v10 19/77] target/riscv: rvv-1.0: configure instructions frank.chang
2021-11-29 3:02 ` [PATCH v10 20/77] target/riscv: rvv-1.0: stride load and store instructions frank.chang
2021-11-29 3:02 ` [PATCH v10 21/77] target/riscv: rvv-1.0: index " frank.chang
2021-11-29 3:02 ` [PATCH v10 22/77] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang
2021-11-29 3:02 ` [PATCH v10 23/77] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang
2021-11-29 3:02 ` [PATCH v10 24/77] target/riscv: rvv-1.0: load/store whole register instructions frank.chang
2021-11-29 3:02 ` [PATCH v10 25/77] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns frank.chang
2021-11-29 3:02 ` [PATCH v10 26/77] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation frank.chang
2021-11-29 3:02 ` [PATCH v10 27/77] target/riscv: rvv-1.0: floating-point square-root instruction frank.chang
2021-11-29 3:02 ` [PATCH v10 28/77] target/riscv: rvv-1.0: floating-point classify instructions frank.chang
2021-11-29 3:02 ` [PATCH v10 29/77] target/riscv: rvv-1.0: count population in mask instruction frank.chang
2021-11-29 3:02 ` [PATCH v10 30/77] target/riscv: rvv-1.0: find-first-set mask bit instruction frank.chang
2021-11-29 3:02 ` [PATCH v10 31/77] target/riscv: rvv-1.0: set-X-first mask bit instructions frank.chang
2021-11-29 3:02 ` [PATCH v10 32/77] target/riscv: rvv-1.0: iota instruction frank.chang
2021-11-29 3:02 ` [PATCH v10 33/77] target/riscv: rvv-1.0: element index instruction frank.chang
2021-11-29 3:02 ` [PATCH v10 34/77] target/riscv: rvv-1.0: allow load element with sign-extended frank.chang
2021-11-29 3:02 ` [PATCH v10 35/77] target/riscv: rvv-1.0: register gather instructions frank.chang
2021-11-29 3:02 ` [PATCH v10 36/77] target/riscv: rvv-1.0: integer scalar move instructions frank.chang
2021-11-29 3:02 ` [PATCH v10 37/77] target/riscv: rvv-1.0: floating-point move instruction frank.chang
2021-11-29 3:02 ` [PATCH v10 38/77] target/riscv: rvv-1.0: floating-point scalar move instructions frank.chang
2021-11-29 3:02 ` [PATCH v10 39/77] target/riscv: rvv-1.0: whole register " frank.chang
2021-11-29 3:03 ` [PATCH v10 40/77] target/riscv: rvv-1.0: integer extension instructions frank.chang
2021-11-29 3:03 ` [PATCH v10 41/77] target/riscv: rvv-1.0: single-width averaging add and subtract instructions frank.chang
2021-11-29 3:03 ` [PATCH v10 42/77] target/riscv: rvv-1.0: single-width bit shift instructions frank.chang
2021-11-29 3:03 ` [PATCH v10 43/77] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow frank.chang
2021-11-29 3:03 ` [PATCH v10 44/77] target/riscv: rvv-1.0: narrowing integer right shift instructions frank.chang
2021-11-29 3:03 ` [PATCH v10 45/77] target/riscv: rvv-1.0: widening integer multiply-add instructions frank.chang
2021-11-29 3:03 ` [PATCH v10 46/77] target/riscv: rvv-1.0: single-width saturating add and subtract instructions frank.chang
2021-11-29 3:03 ` [PATCH v10 47/77] target/riscv: rvv-1.0: integer comparison instructions frank.chang
2021-11-29 3:03 ` [PATCH v10 48/77] target/riscv: rvv-1.0: floating-point compare instructions frank.chang
2021-11-29 3:03 ` [PATCH v10 49/77] target/riscv: rvv-1.0: mask-register logical instructions frank.chang
2021-11-29 3:03 ` [PATCH v10 50/77] target/riscv: rvv-1.0: slide instructions frank.chang
2021-11-29 3:03 ` [PATCH v10 51/77] target/riscv: rvv-1.0: floating-point " frank.chang
2021-11-29 3:03 ` [PATCH v10 52/77] target/riscv: rvv-1.0: narrowing fixed-point clip instructions frank.chang
2021-11-29 3:03 ` [PATCH v10 53/77] target/riscv: rvv-1.0: single-width floating-point reduction frank.chang
2021-11-29 3:03 ` [PATCH v10 54/77] target/riscv: rvv-1.0: widening floating-point reduction instructions frank.chang
2021-11-29 3:03 ` [PATCH v10 55/77] target/riscv: rvv-1.0: single-width scaling shift instructions frank.chang
2021-11-29 3:03 ` [PATCH v10 56/77] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add frank.chang
2021-11-29 3:03 ` [PATCH v10 57/77] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf frank.chang
2021-11-29 3:03 ` [PATCH v10 58/77] target/riscv: rvv-1.0: remove integer extract instruction frank.chang
2021-11-29 3:03 ` [PATCH v10 59/77] target/riscv: rvv-1.0: floating-point min/max instructions frank.chang
2021-11-29 3:03 ` [PATCH v10 60/77] target/riscv: introduce floating-point rounding mode enum frank.chang
2021-11-29 3:03 ` [PATCH v10 61/77] target/riscv: rvv-1.0: floating-point/integer type-convert instructions frank.chang
2021-11-29 3:03 ` [PATCH v10 62/77] target/riscv: rvv-1.0: widening floating-point/integer type-convert frank.chang
2021-11-29 3:03 ` [PATCH v10 63/77] target/riscv: add "set round to odd" rounding mode helper function frank.chang
2021-11-29 3:03 ` [PATCH v10 64/77] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert frank.chang
2021-11-29 3:03 ` [PATCH v10 65/77] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits frank.chang
2021-11-29 3:03 ` [PATCH v10 66/77] target/riscv: rvv-1.0: implement vstart CSR frank.chang
2021-11-29 3:03 ` [PATCH v10 67/77] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid frank.chang
2021-11-29 3:03 ` [PATCH v10 68/77] target/riscv: gdb: support vector registers for rv64 & rv32 frank.chang
2021-11-29 3:03 ` [PATCH v10 69/77] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction frank.chang
2021-12-08 3:32 ` Alistair Francis
2021-11-29 3:03 ` [PATCH v10 70/77] target/riscv: rvv-1.0: floating-point reciprocal " frank.chang
2021-12-08 3:38 ` Alistair Francis
2021-11-29 3:03 ` [PATCH v10 71/77] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 frank.chang
2021-11-29 3:03 ` [PATCH v10 72/77] target/riscv: rvv-1.0: add vsetivli instruction frank.chang
2021-11-29 3:03 ` [PATCH v10 73/77] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() frank.chang
2021-11-29 3:03 ` [PATCH v10 74/77] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns frank.chang
2021-11-29 3:03 ` [PATCH v10 75/77] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm frank.chang
2021-11-29 3:03 ` [PATCH v10 76/77] target/riscv: rvv-1.0: update opivv_vadc_check() comment frank.chang
2021-11-29 3:03 ` [PATCH v10 77/77] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions frank.chang
2021-12-08 3:44 ` Alistair Francis
2021-12-08 6:39 ` [PATCH v10 00/77] support vector extension v1.0 Alistair Francis
2021-12-10 7:35 ` Frank Chang
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