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Wed, 01 Oct 2025 18:25:30 -0700 (PDT) MIME-Version: 1.0 References: <20251001094859.2030290-1-djordje.todorovic@htecgroup.com> <20251001094859.2030290-3-djordje.todorovic@htecgroup.com> In-Reply-To: <20251001094859.2030290-3-djordje.todorovic@htecgroup.com> From: Alistair Francis Date: Thu, 2 Oct 2025 11:25:04 +1000 X-Gm-Features: AS18NWCWdi9llyalL4EjQGXU9hZZQOIk1N6p8JUpwb_BnpwXvDYDau9Z2iLW8YI Message-ID: Subject: Re: [PATCH v9 02/13] target/riscv: Add cpu_set_exception_base To: Djordje Todorovic Cc: "qemu-devel@nongnu.org" , "qemu-riscv@nongnu.org" , "cfu@mips.com" , "mst@redhat.com" , "marcel.apfelbaum@gmail.com" , "dbarboza@ventanamicro.com" , "philmd@linaro.org" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=alistair23@gmail.com; helo=mail-ed1-x536.google.com X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Oct 1, 2025 at 7:49=E2=80=AFPM Djordje Todorovic wrote: > > Add a new function, so we can change reset vector from platforms > during runtime. > > Signed-off-by: Chao-ying Fu > Signed-off-by: Djordje Todorovic > Reviewed-by: Daniel Henrique Barboza > --- > target/riscv/cpu.c | 14 ++++++++++++++ > target/riscv/cpu.h | 4 ++++ > 2 files changed, 18 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index d055ddf462..74728c5371 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -73,6 +73,20 @@ bool riscv_cpu_option_set(const char *optname) > return g_hash_table_contains(general_user_opts, optname); > } > > +#ifndef CONFIG_USER_ONLY > +void cpu_set_exception_base(int vp_index, target_ulong address) This should probably have some documentation saying that it's only for runtime usage Alistair > +{ > + CPUState *cpu_state =3D qemu_get_cpu(vp_index); > + if (cpu_state =3D=3D NULL) { > + qemu_log_mask(LOG_GUEST_ERROR, > + "cpu_set_exception_base: invalid vp_index: %u", > + vp_index); > + } > + RISCVCPU *vp =3D RISCV_CPU(cpu_state); > + vp->env.resetvec =3D address; > +} > +#endif > + > static void riscv_cpu_cfg_merge(RISCVCPUConfig *dest, const RISCVCPUConf= ig *src) > { > #define BOOL_FIELD(x) dest->x |=3D src->x; > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 4a862da615..34751bd414 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -672,6 +672,10 @@ G_NORETURN void riscv_raise_exception(CPURISCVState = *env, > target_ulong riscv_cpu_get_fflags(CPURISCVState *env); > void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); > > +#ifndef CONFIG_USER_ONLY > +void cpu_set_exception_base(int vp_index, target_ulong address); > +#endif > + > FIELD(TB_FLAGS, MEM_IDX, 0, 3) > FIELD(TB_FLAGS, FS, 3, 2) > /* Vector flags */ > -- > 2.34.1