From: Alistair Francis <alistair23@gmail.com>
To: Max Chou <max.chou@sifive.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Subject: Re: [PATCH v2 2/2] target/riscv: rvv: Modify minimum VLEN according to enabled vector extensions
Date: Mon, 29 Sep 2025 10:59:25 +1000 [thread overview]
Message-ID: <CAKmqyKNw17kgo8XJrb0F=NjaPA3J40TBEr_cnagEdcr4NT-NKw@mail.gmail.com> (raw)
In-Reply-To: <20250923090729.1887406-3-max.chou@sifive.com>
On Tue, Sep 23, 2025 at 7:08 PM Max Chou <max.chou@sifive.com> wrote:
>
> According to the RISC-V unprivileged specification, the VLEN should be greater
> or equal to the ELEN. This commit modifies the minimum VLEN based on the vector
> extensions and introduces a check rule for VLEN and ELEN.
>
> Extension Minimum VLEN
> * V 128
> * Zve64[d|f|x] 64
> * Zve32[f|x] 32
>
> Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/tcg/tcg-cpu.c | 19 +++++++++++++++++--
> 1 file changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index a6f60f55ceb..02d99bb0ae9 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -416,12 +416,21 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
> static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
> Error **errp)
> {
> + uint32_t min_vlen;
> uint32_t vlen = cfg->vlenb << 3;
>
> - if (vlen > RV_VLEN_MAX || vlen < 128) {
> + if (riscv_has_ext(env, RVV)) {
> + min_vlen = 128;
> + } else if (cfg->ext_zve64x) {
> + min_vlen = 64;
> + } else if (cfg->ext_zve32x) {
> + min_vlen = 32;
> + }
> +
> + if (vlen > RV_VLEN_MAX || vlen < min_vlen) {
> error_setg(errp,
> "Vector extension implementation only supports VLEN "
> - "in the range [128, %d]", RV_VLEN_MAX);
> + "in the range [%d, %d]", min_vlen, RV_VLEN_MAX);
> return;
> }
>
> @@ -431,6 +440,12 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
> "in the range [8, 64]");
> return;
> }
> +
> + if (vlen < cfg->elen) {
> + error_setg(errp, "Vector extension implementation requires VLEN "
> + "to be greater than or equal to ELEN");
> + return;
> + }
> }
>
> static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
> --
> 2.43.0
>
>
next prev parent reply other threads:[~2025-09-29 1:01 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-23 9:07 [PATCH v2 0/2] riscv: Modify minimum VLEN rule Max Chou
2025-09-23 9:07 ` [PATCH v2 1/2] target/riscv: rvv: Replace checking V by checking Zve32x Max Chou
2025-09-29 0:58 ` Alistair Francis
2025-09-23 9:07 ` [PATCH v2 2/2] target/riscv: rvv: Modify minimum VLEN according to enabled vector extensions Max Chou
2025-09-29 0:59 ` Alistair Francis [this message]
2025-09-29 1:15 ` [PATCH v2 0/2] riscv: Modify minimum VLEN rule Alistair Francis
2025-10-04 7:44 ` Michael Tokarev
2025-10-08 7:13 ` Michael Tokarev
2025-10-08 9:49 ` Max Chou
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