[PATCH v2 0/2] riscv: Modify minimum VLEN rule

[PATCH v2 0/2] riscv: Modify minimum VLEN rule

[Max Chou]

According to the RISC-V unprivileged specification, the VLEN should be greater
or equal to the ELEN. This patchset provides following modifications:

* Replace the checkings of standard V with the checkings of Zve32x
* Introduces a check rule for VLEN and ELEN
* Modifies the minimum VLEN based on the vector extensions

Extension     Minimum VLEN
V                      128
Zve64[d|f|x]            64
Zve32[f|x]              32

v1: 20250627132156.440214-1-max.chou@sifive.com
- Rebase to riscv-to-apply.next branch
- Add patch 1 to replace checking RVV by checking Zve32x

Max Chou (2):
  target/riscv: rvv: Replace checking V by checking Zve32x
  target/riscv: rvv: Modify minimum VLEN according to enabled vector
    extensions

 target/riscv/cpu.c            |  2 +-
 target/riscv/csr.c            |  3 ++-
 target/riscv/machine.c        |  3 ++-
 target/riscv/riscv-qmp-cmds.c |  2 +-
 target/riscv/tcg/tcg-cpu.c    | 21 ++++++++++++++++++---
 5 files changed, 24 insertions(+), 7 deletions(-)

-- 
2.43.0

[PATCH v2 1/2] target/riscv: rvv: Replace checking V by checking Zve32x

[Max Chou]

The Zve32x extension will be applied by the V and Zve* extensions.
Therefore we can replace the original V checking with Zve32x checking for both
the V and Zve* extensions.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/cpu.c            | 2 +-
 target/riscv/csr.c            | 3 ++-
 target/riscv/machine.c        | 3 ++-
 target/riscv/riscv-qmp-cmds.c | 2 +-
 target/riscv/tcg/tcg-cpu.c    | 2 +-
 5 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d055ddf4623..a877018ab0c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -604,7 +604,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
             }
         }
     }
-    if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) {
+    if (riscv_cpu_cfg(env)->ext_zve32x && (flags & CPU_DUMP_VPU)) {
         static const int dump_rvv_csrs[] = {
                     CSR_VSTART,
                     CSR_VXSAT,
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 8842e07a735..5824928d954 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -2004,7 +2004,8 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
     if (riscv_has_ext(env, RVF)) {
         mask |= MSTATUS_FS;
     }
-    if (riscv_has_ext(env, RVV)) {
+
+    if (riscv_cpu_cfg(env)->ext_zve32x) {
         mask |= MSTATUS_VS;
     }
 
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 51e0567ed30..18d790af0d0 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -131,7 +131,8 @@ static bool vector_needed(void *opaque)
     RISCVCPU *cpu = opaque;
     CPURISCVState *env = &cpu->env;
 
-    return riscv_has_ext(env, RVV);
+    return kvm_enabled() ? riscv_has_ext(env, RVV) :
+                           riscv_cpu_cfg(env)->ext_zve32x;
 }
 
 static const VMStateDescription vmstate_vector = {
diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c
index b63de8dd457..c499f9b9a7d 100644
--- a/target/riscv/riscv-qmp-cmds.c
+++ b/target/riscv/riscv-qmp-cmds.c
@@ -342,7 +342,7 @@ int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)
     }
 
     if (reg_is_vreg(name)) {
-        if (!riscv_has_ext(env, RVV)) {
+        if (!riscv_cpu_cfg(env)->ext_zve32x) {
             return -EINVAL;
         }
 
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 78fb2791847..a6f60f55ceb 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -660,7 +660,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
-    if (riscv_has_ext(env, RVV)) {
+    if (cpu->cfg.ext_zve32x) {
         riscv_cpu_validate_v(env, &cpu->cfg, &local_err);
         if (local_err != NULL) {
             error_propagate(errp, local_err);
-- 
2.43.0

Re: [PATCH v2 1/2] target/riscv: rvv: Replace checking V by checking Zve32x

[Alistair Francis]

On Tue, Sep 23, 2025 at 7:09 PM Max Chou <max.chou@sifive.com> wrote:
>
> The Zve32x extension will be applied by the V and Zve* extensions.
> Therefore we can replace the original V checking with Zve32x checking for both
> the V and Zve* extensions.
>
> Signed-off-by: Max Chou <max.chou@sifive.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c            | 2 +-
>  target/riscv/csr.c            | 3 ++-
>  target/riscv/machine.c        | 3 ++-
>  target/riscv/riscv-qmp-cmds.c | 2 +-
>  target/riscv/tcg/tcg-cpu.c    | 2 +-
>  5 files changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d055ddf4623..a877018ab0c 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -604,7 +604,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
>              }
>          }
>      }
> -    if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) {
> +    if (riscv_cpu_cfg(env)->ext_zve32x && (flags & CPU_DUMP_VPU)) {
>          static const int dump_rvv_csrs[] = {
>                      CSR_VSTART,
>                      CSR_VXSAT,
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 8842e07a735..5824928d954 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -2004,7 +2004,8 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
>      if (riscv_has_ext(env, RVF)) {
>          mask |= MSTATUS_FS;
>      }
> -    if (riscv_has_ext(env, RVV)) {
> +
> +    if (riscv_cpu_cfg(env)->ext_zve32x) {
>          mask |= MSTATUS_VS;
>      }
>
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 51e0567ed30..18d790af0d0 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -131,7 +131,8 @@ static bool vector_needed(void *opaque)
>      RISCVCPU *cpu = opaque;
>      CPURISCVState *env = &cpu->env;
>
> -    return riscv_has_ext(env, RVV);
> +    return kvm_enabled() ? riscv_has_ext(env, RVV) :
> +                           riscv_cpu_cfg(env)->ext_zve32x;
>  }
>
>  static const VMStateDescription vmstate_vector = {
> diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c
> index b63de8dd457..c499f9b9a7d 100644
> --- a/target/riscv/riscv-qmp-cmds.c
> +++ b/target/riscv/riscv-qmp-cmds.c
> @@ -342,7 +342,7 @@ int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)
>      }
>
>      if (reg_is_vreg(name)) {
> -        if (!riscv_has_ext(env, RVV)) {
> +        if (!riscv_cpu_cfg(env)->ext_zve32x) {
>              return -EINVAL;
>          }
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 78fb2791847..a6f60f55ceb 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -660,7 +660,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>          return;
>      }
>
> -    if (riscv_has_ext(env, RVV)) {
> +    if (cpu->cfg.ext_zve32x) {
>          riscv_cpu_validate_v(env, &cpu->cfg, &local_err);
>          if (local_err != NULL) {
>              error_propagate(errp, local_err);
> --
> 2.43.0
>
>

[PATCH v2 2/2] target/riscv: rvv: Modify minimum VLEN according to enabled vector extensions

[Max Chou]

According to the RISC-V unprivileged specification, the VLEN should be greater
or equal to the ELEN. This commit modifies the minimum VLEN based on the vector
extensions and introduces a check rule for VLEN and ELEN.

  Extension     Minimum VLEN
* V                      128
* Zve64[d|f|x]            64
* Zve32[f|x]              32

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/tcg/tcg-cpu.c | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index a6f60f55ceb..02d99bb0ae9 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -416,12 +416,21 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
 static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
                                  Error **errp)
 {
+    uint32_t min_vlen;
     uint32_t vlen = cfg->vlenb << 3;
 
-    if (vlen > RV_VLEN_MAX || vlen < 128) {
+    if (riscv_has_ext(env, RVV)) {
+        min_vlen = 128;
+    } else if (cfg->ext_zve64x) {
+        min_vlen = 64;
+    } else if (cfg->ext_zve32x) {
+        min_vlen = 32;
+    }
+
+    if (vlen > RV_VLEN_MAX || vlen < min_vlen) {
         error_setg(errp,
                    "Vector extension implementation only supports VLEN "
-                   "in the range [128, %d]", RV_VLEN_MAX);
+                   "in the range [%d, %d]", min_vlen, RV_VLEN_MAX);
         return;
     }
 
@@ -431,6 +440,12 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
                    "in the range [8, 64]");
         return;
     }
+
+    if (vlen < cfg->elen) {
+        error_setg(errp, "Vector extension implementation requires VLEN "
+                         "to be greater than or equal to ELEN");
+        return;
+    }
 }
 
 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
-- 
2.43.0

Re: [PATCH v2 2/2] target/riscv: rvv: Modify minimum VLEN according to enabled vector extensions

[Alistair Francis]

On Tue, Sep 23, 2025 at 7:08 PM Max Chou <max.chou@sifive.com> wrote:
>
> According to the RISC-V unprivileged specification, the VLEN should be greater
> or equal to the ELEN. This commit modifies the minimum VLEN based on the vector
> extensions and introduces a check rule for VLEN and ELEN.
>
>   Extension     Minimum VLEN
> * V                      128
> * Zve64[d|f|x]            64
> * Zve32[f|x]              32
>
> Signed-off-by: Max Chou <max.chou@sifive.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/tcg/tcg-cpu.c | 19 +++++++++++++++++--
>  1 file changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index a6f60f55ceb..02d99bb0ae9 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -416,12 +416,21 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
>  static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
>                                   Error **errp)
>  {
> +    uint32_t min_vlen;
>      uint32_t vlen = cfg->vlenb << 3;
>
> -    if (vlen > RV_VLEN_MAX || vlen < 128) {
> +    if (riscv_has_ext(env, RVV)) {
> +        min_vlen = 128;
> +    } else if (cfg->ext_zve64x) {
> +        min_vlen = 64;
> +    } else if (cfg->ext_zve32x) {
> +        min_vlen = 32;
> +    }
> +
> +    if (vlen > RV_VLEN_MAX || vlen < min_vlen) {
>          error_setg(errp,
>                     "Vector extension implementation only supports VLEN "
> -                   "in the range [128, %d]", RV_VLEN_MAX);
> +                   "in the range [%d, %d]", min_vlen, RV_VLEN_MAX);
>          return;
>      }
>
> @@ -431,6 +440,12 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
>                     "in the range [8, 64]");
>          return;
>      }
> +
> +    if (vlen < cfg->elen) {
> +        error_setg(errp, "Vector extension implementation requires VLEN "
> +                         "to be greater than or equal to ELEN");
> +        return;
> +    }
>  }
>
>  static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
> --
> 2.43.0
>
>

Re: [PATCH v2 0/2] riscv: Modify minimum VLEN rule

[Alistair Francis]

On Tue, Sep 23, 2025 at 7:09 PM Max Chou <max.chou@sifive.com> wrote:
>
> According to the RISC-V unprivileged specification, the VLEN should be greater
> or equal to the ELEN. This patchset provides following modifications:
>
> * Replace the checkings of standard V with the checkings of Zve32x
> * Introduces a check rule for VLEN and ELEN
> * Modifies the minimum VLEN based on the vector extensions
>
> Extension     Minimum VLEN
> V                      128
> Zve64[d|f|x]            64
> Zve32[f|x]              32
>
> v1: 20250627132156.440214-1-max.chou@sifive.com
> - Rebase to riscv-to-apply.next branch
> - Add patch 1 to replace checking RVV by checking Zve32x
>
> Max Chou (2):
>   target/riscv: rvv: Replace checking V by checking Zve32x
>   target/riscv: rvv: Modify minimum VLEN according to enabled vector
>     extensions

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/cpu.c            |  2 +-
>  target/riscv/csr.c            |  3 ++-
>  target/riscv/machine.c        |  3 ++-
>  target/riscv/riscv-qmp-cmds.c |  2 +-
>  target/riscv/tcg/tcg-cpu.c    | 21 ++++++++++++++++++---
>  5 files changed, 24 insertions(+), 7 deletions(-)
>
> --
> 2.43.0
>
>

Re: [PATCH v2 0/2] riscv: Modify minimum VLEN rule

[Michael Tokarev]

On 9/23/25 12:07, Max Chou wrote:
> According to the RISC-V unprivileged specification, the VLEN should be greater
> or equal to the ELEN. This patchset provides following modifications:
> 
> * Replace the checkings of standard V with the checkings of Zve32x
> * Introduces a check rule for VLEN and ELEN
> * Modifies the minimum VLEN based on the vector extensions
> 
> Extension     Minimum VLEN
> V                      128
> Zve64[d|f|x]            64
> Zve32[f|x]              32
> 
> v1: 20250627132156.440214-1-max.chou@sifive.com
> - Rebase to riscv-to-apply.next branch
> - Add patch 1 to replace checking RVV by checking Zve32x
> 
> Max Chou (2):
>    target/riscv: rvv: Replace checking V by checking Zve32x
>    target/riscv: rvv: Modify minimum VLEN according to enabled vector
>      extensions

Is this a qemu-stable material?
(these changes does not apply directly to 10.1.x, probably the
MonitorDef change in the first patch here can be dropped)

Thanks,

/mjt

Re: [PATCH v2 0/2] riscv: Modify minimum VLEN rule

[Michael Tokarev]

On 10/4/25 10:44, Michael Tokarev wrote:
> On 9/23/25 12:07, Max Chou wrote:
>> According to the RISC-V unprivileged specification, the VLEN should be 
>> greater
>> or equal to the ELEN. This patchset provides following modifications:
>>
>> * Replace the checkings of standard V with the checkings of Zve32x
>> * Introduces a check rule for VLEN and ELEN
>> * Modifies the minimum VLEN based on the vector extensions
>>
>> Extension     Minimum VLEN
>> V                      128
>> Zve64[d|f|x]            64
>> Zve32[f|x]              32
>>
>> v1: 20250627132156.440214-1-max.chou@sifive.com
>> - Rebase to riscv-to-apply.next branch
>> - Add patch 1 to replace checking RVV by checking Zve32x
>>
>> Max Chou (2):
>>    target/riscv: rvv: Replace checking V by checking Zve32x
>>    target/riscv: rvv: Modify minimum VLEN according to enabled vector
>>      extensions
> 
> Is this a qemu-stable material?
> (these changes does not apply directly to 10.1.x, probably the
> MonitorDef change in the first patch here can be dropped)

Hi!

I've picked this series for qemu-stable 10.0 and 10.1 series.
I still haven't received any reply from y previous email asking
about these, so I'm a bit uncomfortable by picking this up for
stable.  But I'm releasing two stable releases today with these
patches in.

Thanks,

/mjt

Re: [PATCH v2 0/2] riscv: Modify minimum VLEN rule

[Max Chou]

[-- Attachment #1: Type: text/plain, Size: 2050 bytes --]

Hi Michael,

Apologies for the delayed response to your question about qemu-stable.
Yes, I believe this patchset is appropriate for qemu-stable material.
The changes fix the VLEN minimum value to properly align with the RISC-V
specification requirements (VLEN >= ELEN), which could affect the
correctness of RISC-V vector extension behavior in QEMU.

Thank you for picking this up for the stable 10.0 and 10.1 releases.
This series is based on the riscv-to-apply.next branch (the VERSION file
shows 10.1.50).

Thanks,
Max


On Wed, Oct 8, 2025 at 3:13 PM Michael Tokarev <mjt@tls.msk.ru> wrote:

> On 10/4/25 10:44, Michael Tokarev wrote:
> > On 9/23/25 12:07, Max Chou wrote:
> >> According to the RISC-V unprivileged specification, the VLEN should be
> >> greater
> >> or equal to the ELEN. This patchset provides following modifications:
> >>
> >> * Replace the checkings of standard V with the checkings of Zve32x
> >> * Introduces a check rule for VLEN and ELEN
> >> * Modifies the minimum VLEN based on the vector extensions
> >>
> >> Extension     Minimum VLEN
> >> V                      128
> >> Zve64[d|f|x]            64
> >> Zve32[f|x]              32
> >>
> >> v1: 20250627132156.440214-1-max.chou@sifive.com
> >> - Rebase to riscv-to-apply.next branch
> >> - Add patch 1 to replace checking RVV by checking Zve32x
> >>
> >> Max Chou (2):
> >>    target/riscv: rvv: Replace checking V by checking Zve32x
> >>    target/riscv: rvv: Modify minimum VLEN according to enabled vector
> >>      extensions
> >
> > Is this a qemu-stable material?
> > (these changes does not apply directly to 10.1.x, probably the
> > MonitorDef change in the first patch here can be dropped)
>
> Hi!
>
> I've picked this series for qemu-stable 10.0 and 10.1 series.
> I still haven't received any reply from y previous email asking
> about these, so I'm a bit uncomfortable by picking this up for
> stable.  But I'm releasing two stable releases today with these
> patches in.
>
> Thanks,
>
> /mjt
>

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