From: Alistair Francis <alistair23@gmail.com>
To: Hesham Almatary <Hesham.Almatary@cl.cam.ac.uk>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Palmer Dabbelt <palmer@sifive.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <Alistair.Francis@wdc.com>
Subject: Re: [Qemu-devel] [PATCHv4 4/6] RISC-V: Check PMP during Page Table Walks
Date: Wed, 5 Jun 2019 14:04:46 -0700 [thread overview]
Message-ID: <CAKmqyKNwec3HaNZ_=vsA1eYa3yjRWe8Q9ZaNcQ9AXZcGvbsQdw@mail.gmail.com> (raw)
In-Reply-To: <20190530135135.19715-4-Hesham.Almatary@cl.cam.ac.uk>
On Thu, May 30, 2019 at 6:52 AM Hesham Almatary
<Hesham.Almatary@cl.cam.ac.uk> wrote:
>
> The PMP should be checked when doing a page table walk, and report access
> fault exception if the to-be-read PTE failed the PMP check.
>
> Suggested-by: Jonathan Behrens <fintelia@gmail.com>
> Signed-off-by: Hesham Almatary <Hesham.Almatary@cl.cam.ac.uk>
> ---
> target/riscv/cpu.h | 1 +
> target/riscv/cpu_helper.c | 10 +++++++++-
> 2 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index c17184f4e4..ab3ba3f15a 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -94,6 +94,7 @@ enum {
> #define PRIV_VERSION_1_09_1 0x00010901
> #define PRIV_VERSION_1_10_0 0x00011000
>
> +#define TRANSLATE_PMP_FAIL 2
> #define TRANSLATE_FAIL 1
> #define TRANSLATE_SUCCESS 0
> #define NB_MMU_MODES 4
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 5a1cd7cf96..00bc4f1712 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -211,6 +211,12 @@ restart:
>
> /* check that physical address of PTE is legal */
> target_ulong pte_addr = base + idx * ptesize;
> +
> + if (riscv_feature(env, RISCV_FEATURE_PMP) &&
> + !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong),
> + 1 << MMU_DATA_LOAD, PRV_S)) {
Shouldn't we be passing mode in here?
Alistair
> + return TRANSLATE_PMP_FAIL;
> + }
> #if defined(TARGET_RISCV32)
> target_ulong pte = ldl_phys(cs->as, pte_addr);
> #elif defined(TARGET_RISCV64)
> @@ -413,8 +419,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> (ret == TRANSLATE_SUCCESS) &&
> !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type,
> mode)) {
> + ret = TRANSLATE_PMP_FAIL;
> + }
> + if (ret == TRANSLATE_PMP_FAIL) {
> pmp_violation = true;
> - ret = TRANSLATE_FAIL;
> }
> if (ret == TRANSLATE_SUCCESS) {
> tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK,
> --
> 2.17.1
>
>
next prev parent reply other threads:[~2019-06-05 21:17 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-30 13:51 [Qemu-devel] [PATCHv4 1/6] RISC-V: Only Check PMP if MMU translation succeeds Hesham Almatary
2019-05-30 13:51 ` [Qemu-devel] [PATCHv4 2/6] RISC-V: Raise access fault exceptions on PMP violations Hesham Almatary
2019-05-30 13:51 ` [Qemu-devel] [PATCHv4 3/6] RISC-V: Check for the effective memory privilege mode during PMP checks Hesham Almatary
2019-06-05 21:02 ` Alistair Francis
2019-05-30 13:51 ` [Qemu-devel] [PATCHv4 4/6] RISC-V: Check PMP during Page Table Walks Hesham Almatary
2019-06-05 21:04 ` Alistair Francis [this message]
2019-06-05 22:58 ` Hesham Almatary
2019-06-06 22:59 ` Alistair Francis
2019-05-30 13:51 ` [Qemu-devel] [PATCHv4 5/6] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off Hesham Almatary
2019-05-30 13:51 ` [Qemu-devel] [PATCHv4 6/6] RISC-V: Fix a PMP check with the correct access size Hesham Almatary
-- strict thread matches above, loose matches on Subject: below --
2019-06-27 12:18 [Qemu-devel] [PATCHv4 1/6] RISC-V: Only Check PMP if MMU translation succeeds Hesham Almatary
2019-06-27 12:18 ` [Qemu-devel] [PATCHv4 4/6] RISC-V: Check PMP during Page Table Walks Hesham Almatary
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