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From: Alistair Francis <alistair23@gmail.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
	alistair.francis@wdc.com,  liwei1518@gmail.com,
	zhiwei_liu@linux.alibaba.com, palmer@dabbelt.com
Subject: Re: [PATCH RESEND v2 3/3] target/riscv/cpu.c: do better with 'named features' doc
Date: Thu, 5 Jun 2025 13:43:41 +1000	[thread overview]
Message-ID: <CAKmqyKNxaeFKoX6yO94e7QZApNuDYcdjOrZVCprrz-=3MfeJLg@mail.gmail.com> (raw)
In-Reply-To: <20250604174329.1147549-4-dbarboza@ventanamicro.com>

On Thu, Jun 5, 2025 at 3:45 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Most of the named features are added directly in isa_edata_arr[], some
> of them are also added in riscv_cpu_named_features(). There is a reason
> for that, and the existing docs can do better explaining it.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Message-ID: <20250529202315.1684198-4-dbarboza@ventanamicro.com>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 14 ++++++++++++--
>  1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index c1bcf60988..758f254c15 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1378,13 +1378,23 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
>   * 'Named features' is the name we give to extensions that we
>   * don't want to expose to users. They are either immutable
>   * (always enabled/disable) or they'll vary depending on
> - * the resulting CPU state. They have riscv,isa strings
> - * and priv_ver like regular extensions.
> + * the resulting CPU state.
> + *
> + * Some of them are always enabled depending on priv version
> + * of the CPU and are declared directly in isa_edata_arr[].
> + * The ones listed here have special checks during finalize()
> + * time and require their own flags like regular extensions.
> + * See riscv_cpu_update_named_features() for more info.
>   */
>  const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
>      MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
>      MULTI_EXT_CFG_BOOL("ssstateen", ext_ssstateen, true),
>      MULTI_EXT_CFG_BOOL("sha", ext_sha, true),
> +
> +    /*
> +     * 'ziccrse' has its own flag because the KVM driver
> +     * wants to enable/disable it on its own accord.
> +     */
>      MULTI_EXT_CFG_BOOL("ziccrse", ext_ziccrse, true),
>
>      { },
> --
> 2.49.0
>
>


      reply	other threads:[~2025-06-05  3:44 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-04 17:43 [PATCH RESEND v2 0/3] target/riscv: add missing named features Daniel Henrique Barboza
2025-06-04 17:43 ` [PATCH RESEND v2 1/3] target/riscv/cpu.c: add 'sdtrig' in riscv,isa Daniel Henrique Barboza
2025-06-05  3:37   ` [PATCH RESEND v2 1/3] target/riscv/cpu.c: add 'sdtrig' in riscv, isa Alistair Francis
2025-06-04 17:43 ` [PATCH RESEND v2 2/3] target/riscv/cpu.c: add 'ssstrict' to " Daniel Henrique Barboza
2025-06-04 17:43 ` [PATCH RESEND v2 3/3] target/riscv/cpu.c: do better with 'named features' doc Daniel Henrique Barboza
2025-06-05  3:43   ` Alistair Francis [this message]

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