[PATCH v5 0/4] RISC-V: Modularize common match conditions for trigger

[PATCH v5 0/4] RISC-V: Modularize common match conditions for trigger

[Alvin Chang via]

According to RISC-V Debug specification ratified version 0.13 [1]
(also applied to version 1.0 [2] but it has not been ratified yet), the
enabled privilege levels of the trigger is common match conditions for
all the types of the trigger.

This series modularize the code for checking the privilege levels of
type 2/3/6 triggers by implementing functions trigger_common_match()
and trigger_priv_match().

Additional match conditions, such as CSR tcontrol and textra, can be
further implemented into trigger_common_match() in the future.

[1]: https://github.com/riscv/riscv-debug-spec/releases/tag/task_group_vote
[2]: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0.0-rc1-asciidoc

Changes from v4:
- Rebasing on riscv-to-apply.next 

Changes from v3:
- Change this series to target Debug Spec. version 0.13

Changes from v2:
- Explicitly mention the targeting version of RISC-V Debug Spec.

Changes from v1:
- Fix typo
- Add commit description for changing behavior of looping the triggers
  when we check type 2 triggers.

Alvin Chang (4):
  target/riscv: Add functions for common matching conditions of trigger
  target/riscv: Apply modularized matching conditions for breakpoint
  target/riscv: Apply modularized matching conditions for watchpoint
  target/riscv: Apply modularized matching conditions for icount trigger

 target/riscv/debug.c | 129 ++++++++++++++++++++++++++++---------------
 1 file changed, 85 insertions(+), 44 deletions(-)

-- 
2.34.1

[PATCH v5 1/4] target/riscv: Add functions for common matching conditions of trigger

[Alvin Chang via]

According to RISC-V Debug specification version 0.13 [1] (also applied
to version 1.0 [2] but it has not been ratified yet), there are several
common matching conditions before firing a trigger, including the
enabled privilege levels of the trigger.

This commit adds trigger_common_match() to prepare the common matching
conditions for the type 2/3/6 triggers. For now, we just implement
trigger_priv_match() to check if the enabled privilege levels of the
trigger match CPU's current privilege level.

[1]: https://github.com/riscv/riscv-debug-spec/releases/tag/task_group_vote
[2]: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0.0-rc1-asciidoc

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/debug.c | 70 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 70 insertions(+)

diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index b110370ea6..05e001d041 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -241,6 +241,76 @@ static void do_trigger_action(CPURISCVState *env, target_ulong trigger_index)
     }
 }
 
+/*
+ * Check the privilege level of specific trigger matches CPU's current privilege
+ * level.
+ */
+static bool trigger_priv_match(CPURISCVState *env, trigger_type_t type,
+                               int trigger_index)
+{
+    target_ulong ctrl = env->tdata1[trigger_index];
+
+    switch (type) {
+    case TRIGGER_TYPE_AD_MATCH:
+        /* type 2 trigger cannot be fired in VU/VS mode */
+        if (env->virt_enabled) {
+            return false;
+        }
+        /* check U/S/M bit against current privilege level */
+        if ((ctrl >> 3) & BIT(env->priv)) {
+            return true;
+        }
+        break;
+    case TRIGGER_TYPE_AD_MATCH6:
+        if (env->virt_enabled) {
+            /* check VU/VS bit against current privilege level */
+            if ((ctrl >> 23) & BIT(env->priv)) {
+                return true;
+            }
+        } else {
+            /* check U/S/M bit against current privilege level */
+            if ((ctrl >> 3) & BIT(env->priv)) {
+                return true;
+            }
+        }
+        break;
+    case TRIGGER_TYPE_INST_CNT:
+        if (env->virt_enabled) {
+            /* check VU/VS bit against current privilege level */
+            if ((ctrl >> 25) & BIT(env->priv)) {
+                return true;
+            }
+        } else {
+            /* check U/S/M bit against current privilege level */
+            if ((ctrl >> 6) & BIT(env->priv)) {
+                return true;
+            }
+        }
+        break;
+    case TRIGGER_TYPE_INT:
+    case TRIGGER_TYPE_EXCP:
+    case TRIGGER_TYPE_EXT_SRC:
+        qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n", type);
+        break;
+    case TRIGGER_TYPE_NO_EXIST:
+    case TRIGGER_TYPE_UNAVAIL:
+        qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d does not exist\n",
+                      type);
+        break;
+    default:
+        g_assert_not_reached();
+    }
+
+    return false;
+}
+
+/* Common matching conditions for all types of the triggers. */
+static bool trigger_common_match(CPURISCVState *env, trigger_type_t type,
+                                 int trigger_index)
+{
+    return trigger_priv_match(env, type, trigger_index);
+}
+
 /* type 2 trigger */
 
 static uint32_t type2_breakpoint_size(CPURISCVState *env, target_ulong ctrl)
-- 
2.34.1

Re: [PATCH v5 1/4] target/riscv: Add functions for common matching conditions of trigger

[Alistair Francis]

On Tue, Jun 4, 2024 at 2:42 PM Alvin Chang via <qemu-devel@nongnu.org> wrote:

The `From` address is mangled here. It shows it was sent from the list
instead of your actual email address.

Do you mind looking into your email setup and see if you can fix it?

Alistair

>
> According to RISC-V Debug specification version 0.13 [1] (also applied
> to version 1.0 [2] but it has not been ratified yet), there are several
> common matching conditions before firing a trigger, including the
> enabled privilege levels of the trigger.
>
> This commit adds trigger_common_match() to prepare the common matching
> conditions for the type 2/3/6 triggers. For now, we just implement
> trigger_priv_match() to check if the enabled privilege levels of the
> trigger match CPU's current privilege level.
>
> [1]: https://github.com/riscv/riscv-debug-spec/releases/tag/task_group_vote
> [2]: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0.0-rc1-asciidoc
>
> Signed-off-by: Alvin Chang <alvinga@andestech.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  target/riscv/debug.c | 70 ++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 70 insertions(+)
>
> diff --git a/target/riscv/debug.c b/target/riscv/debug.c
> index b110370ea6..05e001d041 100644
> --- a/target/riscv/debug.c
> +++ b/target/riscv/debug.c
> @@ -241,6 +241,76 @@ static void do_trigger_action(CPURISCVState *env, target_ulong trigger_index)
>      }
>  }
>
> +/*
> + * Check the privilege level of specific trigger matches CPU's current privilege
> + * level.
> + */
> +static bool trigger_priv_match(CPURISCVState *env, trigger_type_t type,
> +                               int trigger_index)
> +{
> +    target_ulong ctrl = env->tdata1[trigger_index];
> +
> +    switch (type) {
> +    case TRIGGER_TYPE_AD_MATCH:
> +        /* type 2 trigger cannot be fired in VU/VS mode */
> +        if (env->virt_enabled) {
> +            return false;
> +        }
> +        /* check U/S/M bit against current privilege level */
> +        if ((ctrl >> 3) & BIT(env->priv)) {
> +            return true;
> +        }
> +        break;
> +    case TRIGGER_TYPE_AD_MATCH6:
> +        if (env->virt_enabled) {
> +            /* check VU/VS bit against current privilege level */
> +            if ((ctrl >> 23) & BIT(env->priv)) {
> +                return true;
> +            }
> +        } else {
> +            /* check U/S/M bit against current privilege level */
> +            if ((ctrl >> 3) & BIT(env->priv)) {
> +                return true;
> +            }
> +        }
> +        break;
> +    case TRIGGER_TYPE_INST_CNT:
> +        if (env->virt_enabled) {
> +            /* check VU/VS bit against current privilege level */
> +            if ((ctrl >> 25) & BIT(env->priv)) {
> +                return true;
> +            }
> +        } else {
> +            /* check U/S/M bit against current privilege level */
> +            if ((ctrl >> 6) & BIT(env->priv)) {
> +                return true;
> +            }
> +        }
> +        break;
> +    case TRIGGER_TYPE_INT:
> +    case TRIGGER_TYPE_EXCP:
> +    case TRIGGER_TYPE_EXT_SRC:
> +        qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n", type);
> +        break;
> +    case TRIGGER_TYPE_NO_EXIST:
> +    case TRIGGER_TYPE_UNAVAIL:
> +        qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d does not exist\n",
> +                      type);
> +        break;
> +    default:
> +        g_assert_not_reached();
> +    }
> +
> +    return false;
> +}
> +
> +/* Common matching conditions for all types of the triggers. */
> +static bool trigger_common_match(CPURISCVState *env, trigger_type_t type,
> +                                 int trigger_index)
> +{
> +    return trigger_priv_match(env, type, trigger_index);
> +}
> +
>  /* type 2 trigger */
>
>  static uint32_t type2_breakpoint_size(CPURISCVState *env, target_ulong ctrl)
> --
> 2.34.1
>
>

RE: [PATCH v5 1/4] target/riscv: Add functions for common matching conditions of trigger

[Alvin Che-Chia Chang(張哲嘉)]

Hi Alistair,

> -----Original Message-----
> From: Alistair Francis <alistair23@gmail.com>
> Sent: Wednesday, June 26, 2024 2:20 PM
> To: Alvin Che-Chia Chang(張哲嘉) <alvinga@andestech.com>
> Cc: qemu-riscv@nongnu.org; qemu-devel@nongnu.org;
> alistair.francis@wdc.com; bin.meng@windriver.com; liwei1518@gmail.com;
> dbarboza@ventanamicro.com; zhiwei_liu@linux.alibaba.com
> Subject: Re: [PATCH v5 1/4] target/riscv: Add functions for common matching
> conditions of trigger
>
> [EXTERNAL MAIL]
>
> On Tue, Jun 4, 2024 at 2:42 PM Alvin Chang via <qemu-devel@nongnu.org>
> wrote:
>
> The `From` address is mangled here. It shows it was sent from the list instead
> of your actual email address.
>
> Do you mind looking into your email setup and see if you can fix it?

I did not add "--from" when I sent the patch files.
And I've just added my name and email address by "git config sendemail.from ......".
Hope it will work next time I send the patch.
Thanks.

Alvin Chang

>
> Alistair
>
> >
> > According to RISC-V Debug specification version 0.13 [1] (also applied
> > to version 1.0 [2] but it has not been ratified yet), there are
> > several common matching conditions before firing a trigger, including
> > the enabled privilege levels of the trigger.
> >
> > This commit adds trigger_common_match() to prepare the common
> matching
> > conditions for the type 2/3/6 triggers. For now, we just implement
> > trigger_priv_match() to check if the enabled privilege levels of the
> > trigger match CPU's current privilege level.
> >
> > [1]:
> > https://github.com/riscv/riscv-debug-spec/releases/tag/task_group_vote
> > [2]:
> > https://github.com/riscv/riscv-debug-spec/releases/tag/1.0.0-rc1-ascii
> > doc
> >
> > Signed-off-by: Alvin Chang <alvinga@andestech.com>
> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> >  target/riscv/debug.c | 70
> > ++++++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 70 insertions(+)
> >
> > diff --git a/target/riscv/debug.c b/target/riscv/debug.c index
> > b110370ea6..05e001d041 100644
> > --- a/target/riscv/debug.c
> > +++ b/target/riscv/debug.c
> > @@ -241,6 +241,76 @@ static void do_trigger_action(CPURISCVState *env,
> target_ulong trigger_index)
> >      }
> >  }
> >
> > +/*
> > + * Check the privilege level of specific trigger matches CPU's
> > +current privilege
> > + * level.
> > + */
> > +static bool trigger_priv_match(CPURISCVState *env, trigger_type_t type,
> > +                               int trigger_index) {
> > +    target_ulong ctrl = env->tdata1[trigger_index];
> > +
> > +    switch (type) {
> > +    case TRIGGER_TYPE_AD_MATCH:
> > +        /* type 2 trigger cannot be fired in VU/VS mode */
> > +        if (env->virt_enabled) {
> > +            return false;
> > +        }
> > +        /* check U/S/M bit against current privilege level */
> > +        if ((ctrl >> 3) & BIT(env->priv)) {
> > +            return true;
> > +        }
> > +        break;
> > +    case TRIGGER_TYPE_AD_MATCH6:
> > +        if (env->virt_enabled) {
> > +            /* check VU/VS bit against current privilege level */
> > +            if ((ctrl >> 23) & BIT(env->priv)) {
> > +                return true;
> > +            }
> > +        } else {
> > +            /* check U/S/M bit against current privilege level */
> > +            if ((ctrl >> 3) & BIT(env->priv)) {
> > +                return true;
> > +            }
> > +        }
> > +        break;
> > +    case TRIGGER_TYPE_INST_CNT:
> > +        if (env->virt_enabled) {
> > +            /* check VU/VS bit against current privilege level */
> > +            if ((ctrl >> 25) & BIT(env->priv)) {
> > +                return true;
> > +            }
> > +        } else {
> > +            /* check U/S/M bit against current privilege level */
> > +            if ((ctrl >> 6) & BIT(env->priv)) {
> > +                return true;
> > +            }
> > +        }
> > +        break;
> > +    case TRIGGER_TYPE_INT:
> > +    case TRIGGER_TYPE_EXCP:
> > +    case TRIGGER_TYPE_EXT_SRC:
> > +        qemu_log_mask(LOG_UNIMP, "trigger type: %d is not
> supported\n", type);
> > +        break;
> > +    case TRIGGER_TYPE_NO_EXIST:
> > +    case TRIGGER_TYPE_UNAVAIL:
> > +        qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d does not
> exist\n",
> > +                      type);
> > +        break;
> > +    default:
> > +        g_assert_not_reached();
> > +    }
> > +
> > +    return false;
> > +}
> > +
> > +/* Common matching conditions for all types of the triggers. */
> > +static bool trigger_common_match(CPURISCVState *env, trigger_type_t
> type,
> > +                                 int trigger_index) {
> > +    return trigger_priv_match(env, type, trigger_index); }
> > +
> >  /* type 2 trigger */
> >
> >  static uint32_t type2_breakpoint_size(CPURISCVState *env,
> > target_ulong ctrl)
> > --
> > 2.34.1
> >
> >
CONFIDENTIALITY NOTICE:

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Copyright ANDES TECHNOLOGY CORPORATION - All Rights Reserved.

Re: [PATCH v5 1/4] target/riscv: Add functions for common matching conditions of trigger

[Alistair Francis]

On Wed, Jun 26, 2024 at 5:27 PM Alvin Che-Chia Chang(張哲嘉)
<alvinga@andestech.com> wrote:
>
> Hi Alistair,
>
> > -----Original Message-----
> > From: Alistair Francis <alistair23@gmail.com>
> > Sent: Wednesday, June 26, 2024 2:20 PM
> > To: Alvin Che-Chia Chang(張哲嘉) <alvinga@andestech.com>
> > Cc: qemu-riscv@nongnu.org; qemu-devel@nongnu.org;
> > alistair.francis@wdc.com; bin.meng@windriver.com; liwei1518@gmail.com;
> > dbarboza@ventanamicro.com; zhiwei_liu@linux.alibaba.com
> > Subject: Re: [PATCH v5 1/4] target/riscv: Add functions for common matching
> > conditions of trigger
> >
> > [EXTERNAL MAIL]
> >
> > On Tue, Jun 4, 2024 at 2:42 PM Alvin Chang via <qemu-devel@nongnu.org>
> > wrote:
> >
> > The `From` address is mangled here. It shows it was sent from the list instead
> > of your actual email address.
> >
> > Do you mind looking into your email setup and see if you can fix it?
>
> I did not add "--from" when I sent the patch files.
> And I've just added my name and email address by "git config sendemail.from ......".

Thanks! Let's see if that works.

This patch fails to compile though, I see this error

../target/riscv/debug.c:308:13: error: ‘trigger_common_match’ defined
but not used [-Werror=unused-function]
 308 | static bool trigger_common_match(CPURISCVState *env, trigger_type_t type,

I'm going to drop this series from my tree. Do you mind resending a
new version with the build failures fixed

Alistair

> Hope it will work next time I send the patch.
> Thanks.
>
> Alvin Chang
>
> >
> > Alistair
> >
> > >
> > > According to RISC-V Debug specification version 0.13 [1] (also applied
> > > to version 1.0 [2] but it has not been ratified yet), there are
> > > several common matching conditions before firing a trigger, including
> > > the enabled privilege levels of the trigger.
> > >
> > > This commit adds trigger_common_match() to prepare the common
> > matching
> > > conditions for the type 2/3/6 triggers. For now, we just implement
> > > trigger_priv_match() to check if the enabled privilege levels of the
> > > trigger match CPU's current privilege level.
> > >
> > > [1]:
> > > https://github.com/riscv/riscv-debug-spec/releases/tag/task_group_vote
> > > [2]:
> > > https://github.com/riscv/riscv-debug-spec/releases/tag/1.0.0-rc1-ascii
> > > doc
> > >
> > > Signed-off-by: Alvin Chang <alvinga@andestech.com>
> > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> > > ---
> > >  target/riscv/debug.c | 70
> > > ++++++++++++++++++++++++++++++++++++++++++++
> > >  1 file changed, 70 insertions(+)
> > >
> > > diff --git a/target/riscv/debug.c b/target/riscv/debug.c index
> > > b110370ea6..05e001d041 100644
> > > --- a/target/riscv/debug.c
> > > +++ b/target/riscv/debug.c
> > > @@ -241,6 +241,76 @@ static void do_trigger_action(CPURISCVState *env,
> > target_ulong trigger_index)
> > >      }
> > >  }
> > >
> > > +/*
> > > + * Check the privilege level of specific trigger matches CPU's
> > > +current privilege
> > > + * level.
> > > + */
> > > +static bool trigger_priv_match(CPURISCVState *env, trigger_type_t type,
> > > +                               int trigger_index) {
> > > +    target_ulong ctrl = env->tdata1[trigger_index];
> > > +
> > > +    switch (type) {
> > > +    case TRIGGER_TYPE_AD_MATCH:
> > > +        /* type 2 trigger cannot be fired in VU/VS mode */
> > > +        if (env->virt_enabled) {
> > > +            return false;
> > > +        }
> > > +        /* check U/S/M bit against current privilege level */
> > > +        if ((ctrl >> 3) & BIT(env->priv)) {
> > > +            return true;
> > > +        }
> > > +        break;
> > > +    case TRIGGER_TYPE_AD_MATCH6:
> > > +        if (env->virt_enabled) {
> > > +            /* check VU/VS bit against current privilege level */
> > > +            if ((ctrl >> 23) & BIT(env->priv)) {
> > > +                return true;
> > > +            }
> > > +        } else {
> > > +            /* check U/S/M bit against current privilege level */
> > > +            if ((ctrl >> 3) & BIT(env->priv)) {
> > > +                return true;
> > > +            }
> > > +        }
> > > +        break;
> > > +    case TRIGGER_TYPE_INST_CNT:
> > > +        if (env->virt_enabled) {
> > > +            /* check VU/VS bit against current privilege level */
> > > +            if ((ctrl >> 25) & BIT(env->priv)) {
> > > +                return true;
> > > +            }
> > > +        } else {
> > > +            /* check U/S/M bit against current privilege level */
> > > +            if ((ctrl >> 6) & BIT(env->priv)) {
> > > +                return true;
> > > +            }
> > > +        }
> > > +        break;
> > > +    case TRIGGER_TYPE_INT:
> > > +    case TRIGGER_TYPE_EXCP:
> > > +    case TRIGGER_TYPE_EXT_SRC:
> > > +        qemu_log_mask(LOG_UNIMP, "trigger type: %d is not
> > supported\n", type);
> > > +        break;
> > > +    case TRIGGER_TYPE_NO_EXIST:
> > > +    case TRIGGER_TYPE_UNAVAIL:
> > > +        qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d does not
> > exist\n",
> > > +                      type);
> > > +        break;
> > > +    default:
> > > +        g_assert_not_reached();
> > > +    }
> > > +
> > > +    return false;
> > > +}
> > > +
> > > +/* Common matching conditions for all types of the triggers. */
> > > +static bool trigger_common_match(CPURISCVState *env, trigger_type_t
> > type,
> > > +                                 int trigger_index) {
> > > +    return trigger_priv_match(env, type, trigger_index); }
> > > +
> > >  /* type 2 trigger */
> > >
> > >  static uint32_t type2_breakpoint_size(CPURISCVState *env,
> > > target_ulong ctrl)
> > > --
> > > 2.34.1
> > >
> > >
> CONFIDENTIALITY NOTICE:
>
> This e-mail (and its attachments) may contain confidential and legally privileged information or information protected from disclosure. If you are not the intended recipient, you are hereby notified that any disclosure, copying, distribution, or use of the information contained herein is strictly prohibited. In this case, please immediately notify the sender by return e-mail, delete the message (and any accompanying documents) and destroy all printed hard copies. Thank you for your cooperation.
>
> Copyright ANDES TECHNOLOGY CORPORATION - All Rights Reserved.

[PATCH v5 2/4] target/riscv: Apply modularized matching conditions for breakpoint

[Alvin Chang via]

We have implemented trigger_common_match(), which checks if the enabled
privilege levels of the trigger match CPU's current privilege level.
Remove the related code in riscv_cpu_debug_check_breakpoint() and invoke
trigger_common_match() to check the privilege levels of the type 2 and
type 6 triggers for the breakpoints.

This commit also changes the behavior of looping the triggers. In
previous implementation, if we have a type 2 trigger and
env->virt_enabled is true, we directly return false to stop the loop.
Now we keep looping all the triggers until we find a matched trigger.

Only the execution bit and the executed PC should be futher checked in
riscv_cpu_debug_check_breakpoint().

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/debug.c | 31 ++++++++-----------------------
 1 file changed, 8 insertions(+), 23 deletions(-)

diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index 05e001d041..11125f333b 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -855,22 +855,18 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
         for (i = 0; i < RV_MAX_TRIGGERS; i++) {
             trigger_type = get_trigger_type(env, i);
 
+            if (!trigger_common_match(env, trigger_type, i)) {
+                continue;
+            }
+
             switch (trigger_type) {
             case TRIGGER_TYPE_AD_MATCH:
-                /* type 2 trigger cannot be fired in VU/VS mode */
-                if (env->virt_enabled) {
-                    return false;
-                }
-
                 ctrl = env->tdata1[i];
                 pc = env->tdata2[i];
 
                 if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
-                    /* check U/S/M bit against current privilege level */
-                    if ((ctrl >> 3) & BIT(env->priv)) {
-                        env->badaddr = pc;
-                        return true;
-                    }
+                    env->badaddr = pc;
+                    return true;
                 }
                 break;
             case TRIGGER_TYPE_AD_MATCH6:
@@ -878,19 +874,8 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                 pc = env->tdata2[i];
 
                 if ((ctrl & TYPE6_EXEC) && (bp->pc == pc)) {
-                    if (env->virt_enabled) {
-                        /* check VU/VS bit against current privilege level */
-                        if ((ctrl >> 23) & BIT(env->priv)) {
-                            env->badaddr = pc;
-                            return true;
-                        }
-                    } else {
-                        /* check U/S/M bit against current privilege level */
-                        if ((ctrl >> 3) & BIT(env->priv)) {
-                            env->badaddr = pc;
-                            return true;
-                        }
-                    }
+                    env->badaddr = pc;
+                    return true;
                 }
                 break;
             default:
-- 
2.34.1

[PATCH v5 3/4] target/riscv: Apply modularized matching conditions for watchpoint

[Alvin Chang via]

We have implemented trigger_common_match(), which checks if the enabled
privilege levels of the trigger match CPU's current privilege level.
Remove the related code in riscv_cpu_debug_check_watchpoint() and invoke
trigger_common_match() to check the privilege levels of the type 2 and
type 6 triggers for the watchpoints.

This commit also changes the behavior of looping the triggers. In
previous implementation, if we have a type 2 trigger and
env->virt_enabled is true, we directly return false to stop the loop.
Now we keep looping all the triggers until we find a matched trigger.

Only load/store bits and loaded/stored address should be further checked
in riscv_cpu_debug_check_watchpoint().

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/debug.c | 26 ++++++--------------------
 1 file changed, 6 insertions(+), 20 deletions(-)

diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index 11125f333b..c290d6002e 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -901,13 +901,12 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
     for (i = 0; i < RV_MAX_TRIGGERS; i++) {
         trigger_type = get_trigger_type(env, i);
 
+        if (!trigger_common_match(env, trigger_type, i)) {
+            continue;
+        }
+
         switch (trigger_type) {
         case TRIGGER_TYPE_AD_MATCH:
-            /* type 2 trigger cannot be fired in VU/VS mode */
-            if (env->virt_enabled) {
-                return false;
-            }
-
             ctrl = env->tdata1[i];
             addr = env->tdata2[i];
             flags = 0;
@@ -920,10 +919,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
             }
 
             if ((wp->flags & flags) && (wp->vaddr == addr)) {
-                /* check U/S/M bit against current privilege level */
-                if ((ctrl >> 3) & BIT(env->priv)) {
-                    return true;
-                }
+                return true;
             }
             break;
         case TRIGGER_TYPE_AD_MATCH6:
@@ -939,17 +935,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
             }
 
             if ((wp->flags & flags) && (wp->vaddr == addr)) {
-                if (env->virt_enabled) {
-                    /* check VU/VS bit against current privilege level */
-                    if ((ctrl >> 23) & BIT(env->priv)) {
-                        return true;
-                    }
-                } else {
-                    /* check U/S/M bit against current privilege level */
-                    if ((ctrl >> 3) & BIT(env->priv)) {
-                        return true;
-                    }
-                }
+                return true;
             }
             break;
         default:
-- 
2.34.1

[PATCH v5 4/4] target/riscv: Apply modularized matching conditions for icount trigger

[Alvin Chang via]

We have implemented trigger_common_match(), which checks if the enabled
privilege levels of the trigger match CPU's current privilege level. We
can invoke trigger_common_match() to check the privilege levels of the
type 3 triggers.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/debug.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index c290d6002e..0b5099ff9a 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -624,7 +624,7 @@ void helper_itrigger_match(CPURISCVState *env)
         if (get_trigger_type(env, i) != TRIGGER_TYPE_INST_CNT) {
             continue;
         }
-        if (check_itrigger_priv(env, i)) {
+        if (!trigger_common_match(env, TRIGGER_TYPE_INST_CNT, i)) {
             continue;
         }
         count = itrigger_get_count(env, i);
-- 
2.34.1

Re: [PATCH v5 0/4] RISC-V: Modularize common match conditions for trigger

[Alistair Francis]

On Tue, Jun 4, 2024 at 2:42 PM Alvin Chang via <qemu-devel@nongnu.org> wrote:
>
> According to RISC-V Debug specification ratified version 0.13 [1]
> (also applied to version 1.0 [2] but it has not been ratified yet), the
> enabled privilege levels of the trigger is common match conditions for
> all the types of the trigger.
>
> This series modularize the code for checking the privilege levels of
> type 2/3/6 triggers by implementing functions trigger_common_match()
> and trigger_priv_match().
>
> Additional match conditions, such as CSR tcontrol and textra, can be
> further implemented into trigger_common_match() in the future.
>
> [1]: https://github.com/riscv/riscv-debug-spec/releases/tag/task_group_vote
> [2]: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0.0-rc1-asciidoc
>
> Changes from v4:
> - Rebasing on riscv-to-apply.next
>
> Changes from v3:
> - Change this series to target Debug Spec. version 0.13
>
> Changes from v2:
> - Explicitly mention the targeting version of RISC-V Debug Spec.
>
> Changes from v1:
> - Fix typo
> - Add commit description for changing behavior of looping the triggers
>   when we check type 2 triggers.
>
> Alvin Chang (4):
>   target/riscv: Add functions for common matching conditions of trigger
>   target/riscv: Apply modularized matching conditions for breakpoint
>   target/riscv: Apply modularized matching conditions for watchpoint
>   target/riscv: Apply modularized matching conditions for icount trigger

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/debug.c | 129 ++++++++++++++++++++++++++++---------------
>  1 file changed, 85 insertions(+), 44 deletions(-)
>
> --
> 2.34.1
>
>