Re: [PATCH v2 0/8] Add support for extension specific disas

[Alistair Francis <alistair23@gmail.com>]

On Tue, May 23, 2023 at 7:38 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Some extensions have conflict encodings, such as
>  * Z*inx reuse the same encodings as normal float point extensions.
>  * Zcm* reuse the some encodings of Zcd.
>  * Custom extensions from different vendors may share the same encodings.
> To resolve this problem, this patchset tries to pass RISCVCPUConfig as disasemble_info.target_info to support extension specific disas, which means that the disas for this extensions is supported only when the related extension is supported.
> This patchset also fixes some style problems in disas/riscv.c.
>
> The port is available here:
> https://github.com/plctlab/plct-qemu/tree/plct-disas-upstream-v2
>
> v2:
>  * Split the RISCVCPUCfg declarations from cpu.h into the new cpu_cfg.h header
> in a separated patch 2 and add a 2023 copyright (Suggested-by: Daniel Henrique Barboza)
>  * Check Zcm* and avoid changing the other lines in patch 4 (Suggested-by: Daniel Henrique Barboza)
>
> Weiwei Li (8):
>   disas: Change type of disassemble_info.target_info to pointer
>   target/riscv: Split RISCVCPUConfig declarations from cpu.h into
>     cpu_cfg.h
>   target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info
>   disas/riscv.c: Support disas for Zcm* extensions
>   disas/riscv.c: Support disas for Z*inx extensions
>   disas/riscv.c: Remove unused decomp_rv32/64 value for vector
>     instructions
>   disas/riscv.c: Fix lines with over 80 characters
>   disas/riscv.c: Remove redundant parentheses

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  disas/riscv.c           | 1194 +++++++++++++++++++++------------------
>  include/disas/dis-asm.h |    2 +-
>  target/riscv/cpu.c      |    1 +
>  target/riscv/cpu.h      |  114 +---
>  target/riscv/cpu_cfg.h  |  136 +++++
>  5 files changed, 785 insertions(+), 662 deletions(-)
>  create mode 100644 target/riscv/cpu_cfg.h
>
> --
> 2.25.1
>
>