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Sun, 23 Feb 2025 19:06:31 -0800 (PST) MIME-Version: 1.0 References: <20241205133003.184581-1-dbarboza@ventanamicro.com> <20241205133003.184581-8-dbarboza@ventanamicro.com> In-Reply-To: <20241205133003.184581-8-dbarboza@ventanamicro.com> From: Alistair Francis Date: Mon, 24 Feb 2025 13:06:05 +1000 X-Gm-Features: AWEUYZnccbpHbiSeXWSyg21XrVbYh4Dbd_xhiitgvQnYIQzFIWv_Pvj0SzLoyAQ Message-ID: Subject: Re: [PATCH for-10.0 07/11] hw/riscv/riscv-iommu: add IOHPMCYCLES mmio write To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Tomasz Jeznach Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::930; envelope-from=alistair23@gmail.com; helo=mail-ua1-x930.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Dec 5, 2024 at 11:34=E2=80=AFPM Daniel Henrique Barboza wrote: > > From: Tomasz Jeznach > > RISCV_IOMMU_REG_IOHPMCYCLES writes are done by > riscv_iommu_process_hpmcycle_write(), called by the mmio write callback > via riscv_iommu_process_hpm_writes(). > > Signed-off-by: Tomasz Jeznach > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/riscv-iommu-hpm.c | 19 +++++++++++++++++++ > hw/riscv/riscv-iommu-hpm.h | 1 + > hw/riscv/riscv-iommu.c | 2 +- > 3 files changed, 21 insertions(+), 1 deletion(-) > > diff --git a/hw/riscv/riscv-iommu-hpm.c b/hw/riscv/riscv-iommu-hpm.c > index 70814b942d..1cea6b1df1 100644 > --- a/hw/riscv/riscv-iommu-hpm.c > +++ b/hw/riscv/riscv-iommu-hpm.c > @@ -262,3 +262,22 @@ void riscv_iommu_process_iocntinh_cy(RISCVIOMMUState= *s, bool prev_cy_inh) > timer_del(s->hpm_timer); > } > } > + > +void riscv_iommu_process_hpmcycle_write(RISCVIOMMUState *s) > +{ > + const uint64_t val =3D riscv_iommu_reg_get64(s, RISCV_IOMMU_REG_IOHP= MCYCLES); > + const uint32_t ovf =3D riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_IOCO= UNTOVF); > + > + /* > + * Clear OF bit in IOCNTOVF if it's being cleared in IOHPMCYCLES reg= ister. > + */ > + if (get_field(ovf, RISCV_IOMMU_IOCOUNTOVF_CY) && > + !get_field(val, RISCV_IOMMU_IOHPMCYCLES_OVF)) { > + riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_IOCOUNTOVF, 0, > + RISCV_IOMMU_IOCOUNTOVF_CY); > + } > + > + s->hpmcycle_val =3D val & ~RISCV_IOMMU_IOHPMCYCLES_OVF; > + s->hpmcycle_prev =3D get_cycles(); > + hpm_setup_timer(s, s->hpmcycle_val); > +} > diff --git a/hw/riscv/riscv-iommu-hpm.h b/hw/riscv/riscv-iommu-hpm.h > index ee888650fb..0cd550975d 100644 > --- a/hw/riscv/riscv-iommu-hpm.h > +++ b/hw/riscv/riscv-iommu-hpm.h > @@ -27,5 +27,6 @@ void riscv_iommu_hpm_incr_ctr(RISCVIOMMUState *s, RISCV= IOMMUContext *ctx, > unsigned event_id); > void riscv_iommu_hpm_timer_cb(void *priv); > void riscv_iommu_process_iocntinh_cy(RISCVIOMMUState *s, bool prev_cy_in= h); > +void riscv_iommu_process_hpmcycle_write(RISCVIOMMUState *s); > > #endif > diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c > index 56ec2d6d42..3bdd88df4a 100644 > --- a/hw/riscv/riscv-iommu.c > +++ b/hw/riscv/riscv-iommu.c > @@ -1934,7 +1934,7 @@ static void riscv_iommu_process_hpm_writes(RISCVIOM= MUState *s, > > case RISCV_IOMMU_REG_IOHPMCYCLES: > case RISCV_IOMMU_REG_IOHPMCYCLES + 4: > - /* not yet implemented */ > + riscv_iommu_process_hpmcycle_write(s); > break; > > case RISCV_IOMMU_REG_IOHPMEVT_BASE ... > -- > 2.47.1 > >