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Sun, 20 Nov 2022 15:35:54 -0800 (PST) MIME-Version: 1.0 References: <20221016124726.102129-1-mchitale@ventanamicro.com> <20221016124726.102129-5-mchitale@ventanamicro.com> In-Reply-To: <20221016124726.102129-5-mchitale@ventanamicro.com> From: Alistair Francis Date: Mon, 21 Nov 2022 09:35:28 +1000 Message-ID: Subject: Re: [PATCH v11 4/5] target/riscv: smstateen check for fcsr To: Mayuresh Chitale Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, Weiwei Li Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::92e; envelope-from=alistair23@gmail.com; helo=mail-ua1-x92e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Sun, Oct 16, 2022 at 11:09 PM Mayuresh Chitale wrote: > > If smstateen is implemented and sstateen0.fcsr is clear then the floating point > operations must return illegal instruction exception or virtual instruction > trap, if relevant. > > Signed-off-by: Mayuresh Chitale > Reviewed-by: Weiwei Li > --- > target/riscv/csr.c | 23 ++++++++++++ > target/riscv/insn_trans/trans_rvf.c.inc | 43 +++++++++++++++++++++-- > target/riscv/insn_trans/trans_rvzfh.c.inc | 12 +++++++ > 3 files changed, 75 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 71236f2b5d..8b25f885ec 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -84,6 +84,10 @@ static RISCVException fs(CPURISCVState *env, int csrno) > !RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { > return RISCV_EXCP_ILLEGAL_INST; > } > + > + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { > + return smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR); > + } > #endif > return RISCV_EXCP_NONE; > } > @@ -2023,6 +2027,9 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno, > target_ulong new_val) > { > uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > + if (!riscv_has_ext(env, RVF)) { > + wr_mask |= SMSTATEEN0_FCSR; > + } > > return write_mstateen(env, csrno, wr_mask, new_val); > } > @@ -2059,6 +2066,10 @@ static RISCVException write_mstateen0h(CPURISCVState *env, int csrno, > { > uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > > + if (!riscv_has_ext(env, RVF)) { > + wr_mask |= SMSTATEEN0_FCSR; > + } > + > return write_mstateenh(env, csrno, wr_mask, new_val); > } > > @@ -2096,6 +2107,10 @@ static RISCVException write_hstateen0(CPURISCVState *env, int csrno, > { > uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > > + if (!riscv_has_ext(env, RVF)) { > + wr_mask |= SMSTATEEN0_FCSR; > + } > + > return write_hstateen(env, csrno, wr_mask, new_val); > } > > @@ -2135,6 +2150,10 @@ static RISCVException write_hstateen0h(CPURISCVState *env, int csrno, > { > uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > > + if (!riscv_has_ext(env, RVF)) { > + wr_mask |= SMSTATEEN0_FCSR; > + } > + > return write_hstateenh(env, csrno, wr_mask, new_val); > } > > @@ -2182,6 +2201,10 @@ static RISCVException write_sstateen0(CPURISCVState *env, int csrno, > { > uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > > + if (!riscv_has_ext(env, RVF)) { > + wr_mask |= SMSTATEEN0_FCSR; > + } > + > return write_sstateen(env, csrno, wr_mask, new_val); > } > > diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc > index a1d3eb52ad..93657680c6 100644 > --- a/target/riscv/insn_trans/trans_rvf.c.inc > +++ b/target/riscv/insn_trans/trans_rvf.c.inc > @@ -24,9 +24,46 @@ > return false; \ > } while (0) > > -#define REQUIRE_ZFINX_OR_F(ctx) do {\ > - if (!ctx->cfg_ptr->ext_zfinx) { \ > - REQUIRE_EXT(ctx, RVF); \ > +#ifndef CONFIG_USER_ONLY > +static inline bool smstateen_fcsr_check(DisasContext *ctx, int index) > +{ > + CPUState *cpu = ctx->cs; > + CPURISCVState *env = cpu->env_ptr; > + uint64_t stateen = env->mstateen[index]; Sorry I missed this the first time around. You can't access env here Richard pointed it out here: https://patchwork.kernel.org/project/qemu-devel/patch/20221117070316.58447-8-liweiwei@iscas.ac.cn/#25095773 I'm going to drop this patch and patch v5 Alistair