From: Alistair Francis <alistair23@gmail.com>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
QEMU Trivial <qemu-trivial@nongnu.org>,
Bin Meng <bin.meng@windriver.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Laurent Vivier <laurent@vivier.eu>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PATCH v2] target/riscv: Do not include 'pmp.h' in user emulation
Date: Mon, 17 May 2021 09:14:12 +1000 [thread overview]
Message-ID: <CAKmqyKO-Jp79AiE2Pubrgi17Tdro2p45y4AucXndFQkvdJGnZQ@mail.gmail.com> (raw)
In-Reply-To: <20210516205333.696094-1-f4bug@amsat.org>
On Mon, May 17, 2021 at 6:53 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Physical Memory Protection is a system feature.
> Avoid polluting the user-mode emulation by its definitions.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7e879fb9ca5..0619b491a42 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -97,7 +97,9 @@ enum {
>
> typedef struct CPURISCVState CPURISCVState;
>
> +#if !defined(CONFIG_USER_ONLY)
> #include "pmp.h"
> +#endif
>
> #define RV_VLEN_MAX 256
>
> --
> 2.26.3
>
>
next prev parent reply other threads:[~2021-05-16 23:16 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-16 20:53 [PATCH v2] target/riscv: Do not include 'pmp.h' in user emulation Philippe Mathieu-Daudé
2021-05-16 20:55 ` Philippe Mathieu-Daudé
2021-05-16 23:14 ` Alistair Francis [this message]
2021-05-17 1:42 ` Bin Meng
2021-05-18 6:33 ` Alistair Francis
2021-06-05 18:59 ` Laurent Vivier
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