* [Qemu-devel] [PATCH v1 1/1] cadence_gem: Correct Marvell PHY SPCFC reset value
@ 2015-09-03 22:10 Alistair Francis
2015-09-03 22:56 ` Edgar E. Iglesias
2015-09-08 14:51 ` Peter Maydell
0 siblings, 2 replies; 7+ messages in thread
From: Alistair Francis @ 2015-09-03 22:10 UTC (permalink / raw)
To: qemu-devel
Cc: edgar.iglesias, peter.maydell, crosthwaitepeter, edgar.iglesias,
alistair.francis
Bit 15 of the PHY Specific Status Register is reserved and
should remain 0. Fix the reset value to ensure that the 15th
bit is not set.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
http://www.marvell.com/transceivers/assets/Marvell-88E3016-Fast-Ethernet.pdf
hw/net/cadence_gem.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 494a346..1127223 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -951,7 +951,7 @@ static void gem_phy_reset(CadenceGEMState *s)
s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00;
s->phy_regs[PHY_REG_EXTSTAT] = 0x3000;
s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078;
- s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0xBC00;
+ s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00;
s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60;
s->phy_regs[PHY_REG_LED] = 0x4100;
s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A;
--
1.7.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH v1 1/1] cadence_gem: Correct Marvell PHY SPCFC reset value
2015-09-03 22:10 [Qemu-devel] [PATCH v1 1/1] cadence_gem: Correct Marvell PHY SPCFC reset value Alistair Francis
@ 2015-09-03 22:56 ` Edgar E. Iglesias
2015-09-04 18:00 ` Alistair Francis
2015-09-08 14:51 ` Peter Maydell
1 sibling, 1 reply; 7+ messages in thread
From: Edgar E. Iglesias @ 2015-09-03 22:56 UTC (permalink / raw)
To: Alistair Francis
Cc: peter.maydell, crosthwaitepeter, qemu-devel, edgar.iglesias
On Thu, Sep 03, 2015 at 03:10:52PM -0700, Alistair Francis wrote:
> Bit 15 of the PHY Specific Status Register is reserved and
> should remain 0. Fix the reset value to ensure that the 15th
> bit is not set.
>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> http://www.marvell.com/transceivers/assets/Marvell-88E3016-Fast-Ethernet.pdf
>
> hw/net/cadence_gem.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
> index 494a346..1127223 100644
> --- a/hw/net/cadence_gem.c
> +++ b/hw/net/cadence_gem.c
> @@ -951,7 +951,7 @@ static void gem_phy_reset(CadenceGEMState *s)
> s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00;
> s->phy_regs[PHY_REG_EXTSTAT] = 0x3000;
> s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078;
> - s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0xBC00;
> + s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00;
> s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60;
> s->phy_regs[PHY_REG_LED] = 0x4100;
> s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A;
> --
> 1.7.1
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH v1 1/1] cadence_gem: Correct Marvell PHY SPCFC reset value
2015-09-03 22:56 ` Edgar E. Iglesias
@ 2015-09-04 18:00 ` Alistair Francis
2015-09-04 18:12 ` Peter Maydell
0 siblings, 1 reply; 7+ messages in thread
From: Alistair Francis @ 2015-09-04 18:00 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: Peter Maydell, Peter Crosthwaite, Edgar Iglesias,
qemu-devel@nongnu.org Developers, Alistair Francis
On Thu, Sep 3, 2015 at 3:56 PM, Edgar E. Iglesias
<edgar.iglesias@xilinx.com> wrote:
> On Thu, Sep 03, 2015 at 03:10:52PM -0700, Alistair Francis wrote:
>> Bit 15 of the PHY Specific Status Register is reserved and
>> should remain 0. Fix the reset value to ensure that the 15th
>> bit is not set.
>>
>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>
> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Thanks Edgar.
Should this go via the ARM queue?
Thanks,
Alistair
>
>
>> ---
>> http://www.marvell.com/transceivers/assets/Marvell-88E3016-Fast-Ethernet.pdf
>>
>> hw/net/cadence_gem.c | 2 +-
>> 1 files changed, 1 insertions(+), 1 deletions(-)
>>
>> diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
>> index 494a346..1127223 100644
>> --- a/hw/net/cadence_gem.c
>> +++ b/hw/net/cadence_gem.c
>> @@ -951,7 +951,7 @@ static void gem_phy_reset(CadenceGEMState *s)
>> s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00;
>> s->phy_regs[PHY_REG_EXTSTAT] = 0x3000;
>> s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078;
>> - s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0xBC00;
>> + s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00;
>> s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60;
>> s->phy_regs[PHY_REG_LED] = 0x4100;
>> s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A;
>> --
>> 1.7.1
>>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH v1 1/1] cadence_gem: Correct Marvell PHY SPCFC reset value
2015-09-04 18:00 ` Alistair Francis
@ 2015-09-04 18:12 ` Peter Maydell
2015-09-04 18:32 ` Alistair Francis
2015-09-04 21:08 ` Edgar E. Iglesias
0 siblings, 2 replies; 7+ messages in thread
From: Peter Maydell @ 2015-09-04 18:12 UTC (permalink / raw)
To: Alistair Francis
Cc: Edgar E. Iglesias, Edgar Iglesias, Peter Crosthwaite,
qemu-devel@nongnu.org Developers
On 4 September 2015 at 19:00, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> On Thu, Sep 3, 2015 at 3:56 PM, Edgar E. Iglesias
> <edgar.iglesias@xilinx.com> wrote:
>> On Thu, Sep 03, 2015 at 03:10:52PM -0700, Alistair Francis wrote:
>>> Bit 15 of the PHY Specific Status Register is reserved and
>>> should remain 0. Fix the reset value to ensure that the 15th
>>> bit is not set.
>>>
>>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>>
>> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>
> Thanks Edgar.
>
> Should this go via the ARM queue?
I was planning to pick it up, unless Edgar would rather
something else.
-- PMM
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH v1 1/1] cadence_gem: Correct Marvell PHY SPCFC reset value
2015-09-04 18:12 ` Peter Maydell
@ 2015-09-04 18:32 ` Alistair Francis
2015-09-04 21:08 ` Edgar E. Iglesias
1 sibling, 0 replies; 7+ messages in thread
From: Alistair Francis @ 2015-09-04 18:32 UTC (permalink / raw)
To: Peter Maydell
Cc: Edgar E. Iglesias, Edgar Iglesias, Peter Crosthwaite,
qemu-devel@nongnu.org Developers, Alistair Francis
On Fri, Sep 4, 2015 at 11:12 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 4 September 2015 at 19:00, Alistair Francis
> <alistair.francis@xilinx.com> wrote:
>> On Thu, Sep 3, 2015 at 3:56 PM, Edgar E. Iglesias
>> <edgar.iglesias@xilinx.com> wrote:
>>> On Thu, Sep 03, 2015 at 03:10:52PM -0700, Alistair Francis wrote:
>>>> Bit 15 of the PHY Specific Status Register is reserved and
>>>> should remain 0. Fix the reset value to ensure that the 15th
>>>> bit is not set.
>>>>
>>>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
>>>
>>> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>>
>> Thanks Edgar.
>>
>> Should this go via the ARM queue?
>
> I was planning to pick it up, unless Edgar would rather
> something else.
Great! Thanks Peter.
That's fine with me, just thought I would check.
Thanks,
Alistair
>
> -- PMM
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH v1 1/1] cadence_gem: Correct Marvell PHY SPCFC reset value
2015-09-04 18:12 ` Peter Maydell
2015-09-04 18:32 ` Alistair Francis
@ 2015-09-04 21:08 ` Edgar E. Iglesias
1 sibling, 0 replies; 7+ messages in thread
From: Edgar E. Iglesias @ 2015-09-04 21:08 UTC (permalink / raw)
To: Peter Maydell
Cc: Edgar Iglesias, Peter Crosthwaite,
qemu-devel@nongnu.org Developers, Alistair Francis
On Fri, Sep 04, 2015 at 07:12:23PM +0100, Peter Maydell wrote:
> On 4 September 2015 at 19:00, Alistair Francis
> <alistair.francis@xilinx.com> wrote:
> > On Thu, Sep 3, 2015 at 3:56 PM, Edgar E. Iglesias
> > <edgar.iglesias@xilinx.com> wrote:
> >> On Thu, Sep 03, 2015 at 03:10:52PM -0700, Alistair Francis wrote:
> >>> Bit 15 of the PHY Specific Status Register is reserved and
> >>> should remain 0. Fix the reset value to ensure that the 15th
> >>> bit is not set.
> >>>
> >>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> >>
> >> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> >
> > Thanks Edgar.
> >
> > Should this go via the ARM queue?
>
> I was planning to pick it up, unless Edgar would rather
> something else.
Sounds good if you take it Peter, thanks!
Best regards,
Edgar
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH v1 1/1] cadence_gem: Correct Marvell PHY SPCFC reset value
2015-09-03 22:10 [Qemu-devel] [PATCH v1 1/1] cadence_gem: Correct Marvell PHY SPCFC reset value Alistair Francis
2015-09-03 22:56 ` Edgar E. Iglesias
@ 2015-09-08 14:51 ` Peter Maydell
1 sibling, 0 replies; 7+ messages in thread
From: Peter Maydell @ 2015-09-08 14:51 UTC (permalink / raw)
To: Alistair Francis
Cc: Edgar Iglesias, Edgar E. Iglesias, Peter Crosthwaite,
QEMU Developers
On 3 September 2015 at 23:10, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> Bit 15 of the PHY Specific Status Register is reserved and
> should remain 0. Fix the reset value to ensure that the 15th
> bit is not set.
>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> ---
> http://www.marvell.com/transceivers/assets/Marvell-88E3016-Fast-Ethernet.pdf
>
> hw/net/cadence_gem.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
> index 494a346..1127223 100644
> --- a/hw/net/cadence_gem.c
> +++ b/hw/net/cadence_gem.c
> @@ -951,7 +951,7 @@ static void gem_phy_reset(CadenceGEMState *s)
> s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00;
> s->phy_regs[PHY_REG_EXTSTAT] = 0x3000;
> s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078;
> - s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0xBC00;
> + s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00;
> s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60;
> s->phy_regs[PHY_REG_LED] = 0x4100;
> s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A;
Applied to target-arm.next, thanks.
-- PMM
^ permalink raw reply [flat|nested] 7+ messages in thread
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2015-09-03 22:10 [Qemu-devel] [PATCH v1 1/1] cadence_gem: Correct Marvell PHY SPCFC reset value Alistair Francis
2015-09-03 22:56 ` Edgar E. Iglesias
2015-09-04 18:00 ` Alistair Francis
2015-09-04 18:12 ` Peter Maydell
2015-09-04 18:32 ` Alistair Francis
2015-09-04 21:08 ` Edgar E. Iglesias
2015-09-08 14:51 ` Peter Maydell
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