From: Alistair Francis <alistair23@gmail.com>
To: Deepak Gupta <debug@rivosinc.com>
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, palmer@dabbelt.com,
Alistair.Francis@wdc.com, laurent@vivier.eu, bmeng.cn@gmail.com,
liwei1518@gmail.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, jim.shu@sifive.com,
andy.chiu@sifive.com, kito.cheng@sifive.com
Subject: Re: [PATCH v10 02/21] linux-user/riscv: set priv for qemu-user and defaults for *envcfg
Date: Wed, 28 Aug 2024 10:10:44 +1000 [thread overview]
Message-ID: <CAKmqyKO2gaVNsSCuvSjTSOjKBOEBJOQC91BK0VDRscJbM-hx7A@mail.gmail.com> (raw)
In-Reply-To: <20240827231906.553327-3-debug@rivosinc.com>
On Wed, Aug 28, 2024 at 9:20 AM Deepak Gupta <debug@rivosinc.com> wrote:
>
> set priv to be PRV_U for qemu-user on riscv. And set default value for
> *envcfg CSR.
>
> Signed-off-by: Deepak Gupta <debug@rivosinc.com>
You can probably just squash this with the previous patch
> ---
> linux-user/riscv/cpu_loop.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c
> index 52c49c2e42..7a68e8717b 100644
> --- a/linux-user/riscv/cpu_loop.c
> +++ b/linux-user/riscv/cpu_loop.c
> @@ -32,6 +32,10 @@ void cpu_loop(CPURISCVState *env)
> int trapnr;
> target_ulong ret;
>
> + env->priv = PRV_U;
> + env->senvcfg = 0;
> + env->menvcfg = 0;
I don't think this is the right place.
This should be handled by a CPU reset, which is still called for linux
user mode.
Alistair
> +
> for (;;) {
> cpu_exec_start(cs);
> trapnr = cpu_exec(cs);
> --
> 2.44.0
>
>
next prev parent reply other threads:[~2024-08-28 0:12 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-27 23:18 [PATCH v10 00/21] riscv support for control flow integrity extensions Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 01/21] target/riscv: expose *envcfg csr and priv to qemu-user as well Deepak Gupta
2024-08-28 0:04 ` Alistair Francis
2024-08-27 23:18 ` [PATCH v10 02/21] linux-user/riscv: set priv for qemu-user and defaults for *envcfg Deepak Gupta
2024-08-28 0:10 ` Alistair Francis [this message]
2024-08-28 0:16 ` Deepak Gupta
2024-08-28 11:36 ` Richard Henderson
2024-08-27 23:18 ` [PATCH v10 03/21] target/riscv: Add zicfilp extension Deepak Gupta
2024-08-27 23:59 ` Alistair Francis
2024-08-27 23:18 ` [PATCH v10 04/21] target/riscv: Introduce elp state and enabling controls for zicfilp Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 05/21] target/riscv: save and restore elp state on priv transitions Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 06/21] target/riscv: additional code information for sw check Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 07/21] target/riscv: tracking indirect branches (fcfi) for zicfilp Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 08/21] target/riscv: zicfilp `lpad` impl and branch tracking Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 09/21] disas/riscv: enable `lpad` disassembly Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 10/21] target/riscv: Expose zicfilp extension as a cpu property Deepak Gupta
2024-08-28 0:02 ` Alistair Francis
2024-08-27 23:18 ` [PATCH v10 11/21] target/riscv: Add zicfiss extension Deepak Gupta
2024-08-28 0:00 ` Alistair Francis
2024-08-27 23:18 ` [PATCH v10 12/21] target/riscv: introduce ssp and enabling controls for zicfiss Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 13/21] target/riscv: tb flag for shadow stack instructions Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 14/21] target/riscv: mmu changes for zicfiss shadow stack protection Deepak Gupta
2024-08-27 23:18 ` [PATCH v10 15/21] target/riscv: AMO operations always raise store/AMO fault Deepak Gupta
2024-08-27 23:19 ` [PATCH v10 16/21] target/riscv: update `decode_save_opc` to store extra word2 Deepak Gupta
2024-08-27 23:19 ` [PATCH v10 17/21] target/riscv: implement zicfiss instructions Deepak Gupta
2024-08-27 23:19 ` [PATCH v10 18/21] target/riscv: compressed encodings for sspush and sspopchk Deepak Gupta
2024-08-27 23:19 ` [PATCH v10 19/21] disas/riscv: enable disassembly for zicfiss instructions Deepak Gupta
2024-08-27 23:19 ` [PATCH v10 20/21] disas/riscv: enable disassembly for compressed sspush/sspopchk Deepak Gupta
2024-08-27 23:19 ` [PATCH v10 21/21] target/riscv: Expose zicfiss extension as a cpu property Deepak Gupta
2024-08-27 23:22 ` [PATCH v10 00/21] riscv support for control flow integrity extensions Deepak Gupta
2024-08-28 0:02 ` Alistair Francis
2024-08-28 0:04 ` Deepak Gupta
2024-08-28 0:11 ` Alistair Francis
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