* [PATCH v9 0/4] RISC-V Smstateen support
@ 2022-09-19 6:29 Mayuresh Chitale
2022-09-19 6:29 ` [PATCH v9 1/4] target/riscv: Add smstateen support Mayuresh Chitale
` (3 more replies)
0 siblings, 4 replies; 11+ messages in thread
From: Mayuresh Chitale @ 2022-09-19 6:29 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Mayuresh Chitale, alistair.francis
This series adds support for the Smstateen specification which provides a
mechanism to plug the potential covert channels which are opened by extensions
that add to processor state that may not get context-switched. Currently access
to *envcfg registers and floating point(fcsr) is controlled via smstateen.
These patches can also be found on riscv_smstateen_v9 branch at:
https://github.com/mdchitale/qemu.git
Changes in v9:
- Rebase to latest riscv-to-apply.next
- Add reviewed by in patches 2 and 4
Changes in v8:
- Rebase to latest riscv-to-apply.next
- Fix m-mode check for hstateen
- Fix return exception type for VU mode
- Improve commit description for patch3
Changes in v7:
- Update smstateen check as per discussion on the following issue:
https://github.com/riscv/riscv-state-enable/issues/9
- Drop the smstateen AIA patch for now.
- Indentation and other fixes
Changes in v6:
- Sync with latest riscv-to-apply.next
- Make separate read/write ops for m/h/s/stateen1/2/3 regs
- Add check for mstateen.staten when reading or using h/s/stateen regs
- Add smstateen fcsr check for all floating point operations
- Move knobs to enable smstateen in a separate patch.
Changes in v5:
- Fix the order in which smstateen extension is added to the
isa_edata_arr as
described in rule #3 the comment.
Changes in v4:
- Fix build issue with riscv32/riscv64-linux-user targets
Changes in v3:
- Fix coding style issues
- Fix *stateen0h index calculation
Changes in v2:
- Make h/s/envcfg bits in m/h/stateen registers as writeable by default.
Mayuresh Chitale (4):
target/riscv: Add smstateen support
target/riscv: smstateen check for h/s/envcfg
target/riscv: smstateen check for fcsr
target/riscv: smstateen knobs
target/riscv/cpu.c | 2 +
target/riscv/cpu.h | 4 +
target/riscv/cpu_bits.h | 37 ++
target/riscv/csr.c | 471 +++++++++++++++++++++-
target/riscv/insn_trans/trans_rvf.c.inc | 40 +-
target/riscv/insn_trans/trans_rvzfh.c.inc | 12 +
target/riscv/machine.c | 21 +
7 files changed, 583 insertions(+), 4 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH v9 1/4] target/riscv: Add smstateen support 2022-09-19 6:29 [PATCH v9 0/4] RISC-V Smstateen support Mayuresh Chitale @ 2022-09-19 6:29 ` Mayuresh Chitale 2022-09-29 0:57 ` weiwei 2022-09-19 6:29 ` [PATCH v9 2/4] target/riscv: smstateen check for h/s/envcfg Mayuresh Chitale ` (2 subsequent siblings) 3 siblings, 1 reply; 11+ messages in thread From: Mayuresh Chitale @ 2022-09-19 6:29 UTC (permalink / raw) To: qemu-devel, qemu-riscv; +Cc: Mayuresh Chitale, alistair.francis Smstateen extension specifies a mechanism to close the potential covert channels that could cause security issues. This patch adds the CSRs defined in the specification and the corresponding predicates and read/write functions. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> --- target/riscv/cpu.h | 4 + target/riscv/cpu_bits.h | 37 ++++ target/riscv/csr.c | 373 ++++++++++++++++++++++++++++++++++++++++ target/riscv/machine.c | 21 +++ 4 files changed, 435 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 06751e1e3e..e407abbf93 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -362,6 +362,9 @@ struct CPUArchState { /* CSRs for execution enviornment configuration */ uint64_t menvcfg; + uint64_t mstateen[SMSTATEEN_MAX_COUNT]; + uint64_t hstateen[SMSTATEEN_MAX_COUNT]; + uint64_t sstateen[SMSTATEEN_MAX_COUNT]; target_ulong senvcfg; uint64_t henvcfg; #endif @@ -437,6 +440,7 @@ struct RISCVCPUConfig { bool ext_ifencei; bool ext_icsr; bool ext_zihintpause; + bool ext_smstateen; bool ext_sstc; bool ext_svinval; bool ext_svnapot; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7be12cac2e..9a3321e27c 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -199,6 +199,12 @@ /* Supervisor Configuration CSRs */ #define CSR_SENVCFG 0x10A +/* Supervisor state CSRs */ +#define CSR_SSTATEEN0 0x10C +#define CSR_SSTATEEN1 0x10D +#define CSR_SSTATEEN2 0x10E +#define CSR_SSTATEEN3 0x10F + /* Supervisor Trap Handling */ #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 @@ -246,6 +252,16 @@ #define CSR_HENVCFG 0x60A #define CSR_HENVCFGH 0x61A +/* Hypervisor state CSRs */ +#define CSR_HSTATEEN0 0x60C +#define CSR_HSTATEEN0H 0x61C +#define CSR_HSTATEEN1 0x60D +#define CSR_HSTATEEN1H 0x61D +#define CSR_HSTATEEN2 0x60E +#define CSR_HSTATEEN2H 0x61E +#define CSR_HSTATEEN3 0x60F +#define CSR_HSTATEEN3H 0x61F + /* Virtual CSRs */ #define CSR_VSSTATUS 0x200 #define CSR_VSIE 0x204 @@ -291,6 +307,27 @@ #define CSR_MENVCFG 0x30A #define CSR_MENVCFGH 0x31A +/* Machine state CSRs */ +#define CSR_MSTATEEN0 0x30C +#define CSR_MSTATEEN0H 0x31C +#define CSR_MSTATEEN1 0x30D +#define CSR_MSTATEEN1H 0x31D +#define CSR_MSTATEEN2 0x30E +#define CSR_MSTATEEN2H 0x31E +#define CSR_MSTATEEN3 0x30F +#define CSR_MSTATEEN3H 0x31F + +/* Common defines for all smstateen */ +#define SMSTATEEN_MAX_COUNT 4 +#define SMSTATEEN0_CS (1ULL << 0) +#define SMSTATEEN0_FCSR (1ULL << 1) +#define SMSTATEEN0_HSCONTXT (1ULL << 57) +#define SMSTATEEN0_IMSIC (1ULL << 58) +#define SMSTATEEN0_AIA (1ULL << 59) +#define SMSTATEEN0_SVSLCT (1ULL << 60) +#define SMSTATEEN0_HSENVCFG (1ULL << 62) +#define SMSTATEEN_STATEEN (1ULL << 63) + /* Enhanced Physical Memory Protection (ePMP) */ #define CSR_MSECCFG 0x747 #define CSR_MSECCFGH 0x757 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index b96db1b62b..bbfdd49abd 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -278,6 +278,72 @@ static RISCVException umode32(CPURISCVState *env, int csrno) return umode(env, csrno); } +static RISCVException mstateen(CPURISCVState *env, int csrno) +{ + CPUState *cs = env_cpu(env); + RISCVCPU *cpu = RISCV_CPU(cs); + + if (!cpu->cfg.ext_smstateen) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return any(env, csrno); +} + +static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base) +{ + CPUState *cs = env_cpu(env); + RISCVCPU *cpu = RISCV_CPU(cs); + + if (!cpu->cfg.ext_smstateen) { + return RISCV_EXCP_ILLEGAL_INST; + } + + if (env->priv < PRV_M) { + if (!(env->mstateen[csrno - base] & SMSTATEEN_STATEEN)) { + return RISCV_EXCP_ILLEGAL_INST; + } + } + + return hmode(env, csrno); +} + +static RISCVException hstateen(CPURISCVState *env, int csrno) +{ + return hstateen_pred(env, csrno, CSR_HSTATEEN0); +} + +static RISCVException hstateenh(CPURISCVState *env, int csrno) +{ + return hstateen_pred(env, csrno, CSR_HSTATEEN0H); +} + +static RISCVException sstateen(CPURISCVState *env, int csrno) +{ + bool virt = riscv_cpu_virt_enabled(env); + int index = csrno - CSR_SSTATEEN0; + CPUState *cs = env_cpu(env); + RISCVCPU *cpu = RISCV_CPU(cs); + + if (!cpu->cfg.ext_smstateen) { + return RISCV_EXCP_ILLEGAL_INST; + } + + if (env->priv < PRV_M) { + if (!(env->mstateen[index] & SMSTATEEN_STATEEN)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + if (virt) { + if (!(env->hstateen[index] & SMSTATEEN_STATEEN)) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + } + } + + return smode(env, csrno); +} + /* Checks if PointerMasking registers could be accessed */ static RISCVException pointer_masking(CPURISCVState *env, int csrno) { @@ -1856,6 +1922,263 @@ static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +static inline void write_smstateen(CPURISCVState *env, uint64_t *reg, + uint64_t wr_mask, uint64_t new_val) +{ + *reg = (*reg & ~wr_mask) | (new_val & wr_mask); +} + +static RISCVException read_mstateen(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->mstateen[csrno - CSR_MSTATEEN0]; + + return RISCV_EXCP_NONE; +} + +static RISCVException write_mstateen(CPURISCVState *env, int csrno, + uint64_t wr_mask, target_ulong new_val) +{ + uint64_t *reg; + + reg = &env->mstateen[csrno - CSR_MSTATEEN0]; + write_smstateen(env, reg, wr_mask, new_val); + + return RISCV_EXCP_NONE; +} + +static RISCVException write_mstateen0(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + uint64_t wr_mask = SMSTATEEN_STATEEN; + + return write_mstateen(env, csrno, wr_mask, new_val); +} + +static RISCVException write_mstateen1(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_mstateen2(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_mstateen3(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException read_mstateenh(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->mstateen[csrno - CSR_MSTATEEN0H] >> 32; + + return RISCV_EXCP_NONE; +} + +static RISCVException write_mstateenh(CPURISCVState *env, int csrno, + uint64_t wr_mask, target_ulong new_val) +{ + uint64_t *reg, val; + + reg = &env->mstateen[csrno - CSR_MSTATEEN0H]; + val = (uint64_t)new_val << 32; + val |= *reg & 0xFFFFFFFF; + write_smstateen(env, reg, wr_mask, val); + + return RISCV_EXCP_NONE; +} + +static RISCVException write_mstateen0h(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + uint64_t wr_mask = SMSTATEEN_STATEEN; + + return write_mstateenh(env, csrno, wr_mask, new_val); +} + +static RISCVException write_mstateen1h(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_mstateen2h(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_mstateen3h(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException read_hstateen(CPURISCVState *env, int csrno, + target_ulong *val) +{ + int index = csrno - CSR_HSTATEEN0; + + *val = env->hstateen[index] & env->mstateen[index]; + + return RISCV_EXCP_NONE; +} + +static RISCVException write_hstateen(CPURISCVState *env, int csrno, + uint64_t mask, target_ulong new_val) +{ + int index = csrno - CSR_HSTATEEN0; + uint64_t *reg, wr_mask; + + reg = &env->hstateen[index]; + wr_mask = env->mstateen[index] & mask; + write_smstateen(env, reg, wr_mask, new_val); + + return RISCV_EXCP_NONE; +} + +static RISCVException write_hstateen0(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + uint64_t wr_mask = SMSTATEEN_STATEEN; + + return write_hstateen(env, csrno, wr_mask, new_val); +} + +static RISCVException write_hstateen1(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_hstateen2(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_hstateen3(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException read_hstateenh(CPURISCVState *env, int csrno, + target_ulong *val) +{ + int index = csrno - CSR_HSTATEEN0H; + + *val = (env->hstateen[index] >> 32) & (env->mstateen[index] >> 32); + + return RISCV_EXCP_NONE; +} + +static RISCVException write_hstateenh(CPURISCVState *env, int csrno, + uint64_t mask, target_ulong new_val) +{ + int index = csrno - CSR_HSTATEEN0H; + uint64_t *reg, wr_mask, val; + + reg = &env->hstateen[index]; + val = (uint64_t)new_val << 32; + val |= *reg & 0xFFFFFFFF; + wr_mask = env->mstateen[index] & mask; + write_smstateen(env, reg, wr_mask, val); + + return RISCV_EXCP_NONE; +} + +static RISCVException write_hstateen0h(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + uint64_t wr_mask = SMSTATEEN_STATEEN; + + return write_hstateenh(env, csrno, wr_mask, new_val); +} + +static RISCVException write_hstateen1h(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_hstateen2h(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_hstateen3h(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException read_sstateen(CPURISCVState *env, int csrno, + target_ulong *val) +{ + bool virt = riscv_cpu_virt_enabled(env); + int index = csrno - CSR_SSTATEEN0; + + *val = env->sstateen[index] & env->mstateen[index]; + if (virt) { + *val &= env->hstateen[index]; + } + + return RISCV_EXCP_NONE; +} + +static RISCVException write_sstateen(CPURISCVState *env, int csrno, + uint64_t mask, target_ulong new_val) +{ + bool virt = riscv_cpu_virt_enabled(env); + int index = csrno - CSR_SSTATEEN0; + uint64_t wr_mask; + uint64_t *reg; + + wr_mask = env->mstateen[index] & mask; + if (virt) { + wr_mask &= env->hstateen[index]; + } + + reg = &env->sstateen[index]; + write_smstateen(env, reg, wr_mask, new_val); + + return RISCV_EXCP_NONE; +} + +static RISCVException write_sstateen0(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + uint64_t wr_mask = SMSTATEEN_STATEEN; + + return write_sstateen(env, csrno, wr_mask, new_val); +} + +static RISCVException write_sstateen1(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_sstateen(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_sstateen2(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_sstateen(env, csrno, SMSTATEEN_STATEEN, new_val); +} + +static RISCVException write_sstateen3(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + return write_sstateen(env, csrno, SMSTATEEN_STATEEN, new_val); +} + static RISCVException rmw_mip64(CPURISCVState *env, int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) @@ -3732,6 +4055,56 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, write_henvcfgh, .min_priv_ver = PRIV_VERSION_1_12_0 }, + /* Smstateen extension CSRs */ + [CSR_MSTATEEN0] = { "mstateen0", mstateen, read_mstateen, write_mstateen0, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MSTATEEN0H] = { "mstateen0h", mstateen, read_mstateenh, + write_mstateen0h, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MSTATEEN1] = { "mstateen1", mstateen, read_mstateen, write_mstateen1, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MSTATEEN1H] = { "mstateen1h", mstateen, read_mstateenh, + write_mstateen1h, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MSTATEEN2] = { "mstateen2", mstateen, read_mstateen, write_mstateen2, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MSTATEEN2H] = { "mstateen2h", mstateen, read_mstateenh, + write_mstateen2h, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MSTATEEN3] = { "mstateen3", mstateen, read_mstateen, write_mstateen3, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MSTATEEN3H] = { "mstateen3h", mstateen, read_mstateenh, + write_mstateen3h, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN0] = { "hstateen0", hstateen, read_hstateen, write_hstateen0, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN0H] = { "hstateen0h", hstateenh, read_hstateenh, + write_hstateen0h, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN1] = { "hstateen1", hstateen, read_hstateen, write_hstateen1, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN1H] = { "hstateen1h", hstateenh, read_hstateenh, + write_hstateen1h, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN2] = { "hstateen2", hstateen, read_hstateen, write_hstateen2, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN2H] = { "hstateen2h", hstateenh, read_hstateenh, + write_hstateen2h, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN3] = { "hstateen3", hstateen, read_hstateen, write_hstateen3, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_HSTATEEN3H] = { "hstateen3h", hstateenh, read_hstateenh, + write_hstateen3h, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_SSTATEEN0] = { "sstateen0", sstateen, read_sstateen, write_sstateen0, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_SSTATEEN1] = { "sstateen1", sstateen, read_sstateen, write_sstateen1, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_SSTATEEN2] = { "sstateen2", sstateen, read_sstateen, write_sstateen2, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_SSTATEEN3] = { "sstateen3", sstateen, read_sstateen, write_sstateen3, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + /* Supervisor Trap Setup */ [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, NULL, read_sstatus_i128 }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 41098f6ad0..18e47f3764 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -263,6 +263,26 @@ static int riscv_cpu_post_load(void *opaque, int version_id) return 0; } +static bool smstateen_needed(void *opaque) +{ + RISCVCPU *cpu = opaque; + + return cpu->cfg.ext_smstateen; +} + +static const VMStateDescription vmstate_smstateen = { + .name = "cpu/smtateen", + .version_id = 1, + .minimum_version_id = 1, + .needed = smstateen_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT64_ARRAY(env.mstateen, RISCVCPU, 4), + VMSTATE_UINT64_ARRAY(env.hstateen, RISCVCPU, 4), + VMSTATE_UINT64_ARRAY(env.sstateen, RISCVCPU, 4), + VMSTATE_END_OF_LIST() + } +}; + static bool envcfg_needed(void *opaque) { RISCVCPU *cpu = opaque; @@ -374,6 +394,7 @@ const VMStateDescription vmstate_riscv_cpu = { &vmstate_kvmtimer, &vmstate_envcfg, &vmstate_debug, + &vmstate_smstateen, NULL } }; -- 2.25.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v9 1/4] target/riscv: Add smstateen support 2022-09-19 6:29 ` [PATCH v9 1/4] target/riscv: Add smstateen support Mayuresh Chitale @ 2022-09-29 0:57 ` weiwei 2022-09-29 1:43 ` Alistair Francis 0 siblings, 1 reply; 11+ messages in thread From: weiwei @ 2022-09-29 0:57 UTC (permalink / raw) To: Mayuresh Chitale, qemu-devel, qemu-riscv; +Cc: alistair.francis, liweiwei On 2022/9/19 14:29, Mayuresh Chitale wrote: > Smstateen extension specifies a mechanism to close > the potential covert channels that could cause security issues. > > This patch adds the CSRs defined in the specification and > the corresponding predicates and read/write functions. > > Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> > --- > target/riscv/cpu.h | 4 + > target/riscv/cpu_bits.h | 37 ++++ > target/riscv/csr.c | 373 ++++++++++++++++++++++++++++++++++++++++ > target/riscv/machine.c | 21 +++ > 4 files changed, 435 insertions(+) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 06751e1e3e..e407abbf93 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -362,6 +362,9 @@ struct CPUArchState { > > /* CSRs for execution enviornment configuration */ > uint64_t menvcfg; > + uint64_t mstateen[SMSTATEEN_MAX_COUNT]; > + uint64_t hstateen[SMSTATEEN_MAX_COUNT]; > + uint64_t sstateen[SMSTATEEN_MAX_COUNT]; > target_ulong senvcfg; > uint64_t henvcfg; > #endif > @@ -437,6 +440,7 @@ struct RISCVCPUConfig { > bool ext_ifencei; > bool ext_icsr; > bool ext_zihintpause; > + bool ext_smstateen; > bool ext_sstc; > bool ext_svinval; > bool ext_svnapot; > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 7be12cac2e..9a3321e27c 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -199,6 +199,12 @@ > /* Supervisor Configuration CSRs */ > #define CSR_SENVCFG 0x10A > > +/* Supervisor state CSRs */ > +#define CSR_SSTATEEN0 0x10C > +#define CSR_SSTATEEN1 0x10D > +#define CSR_SSTATEEN2 0x10E > +#define CSR_SSTATEEN3 0x10F > + > /* Supervisor Trap Handling */ > #define CSR_SSCRATCH 0x140 > #define CSR_SEPC 0x141 > @@ -246,6 +252,16 @@ > #define CSR_HENVCFG 0x60A > #define CSR_HENVCFGH 0x61A > > +/* Hypervisor state CSRs */ > +#define CSR_HSTATEEN0 0x60C > +#define CSR_HSTATEEN0H 0x61C > +#define CSR_HSTATEEN1 0x60D > +#define CSR_HSTATEEN1H 0x61D > +#define CSR_HSTATEEN2 0x60E > +#define CSR_HSTATEEN2H 0x61E > +#define CSR_HSTATEEN3 0x60F > +#define CSR_HSTATEEN3H 0x61F > + > /* Virtual CSRs */ > #define CSR_VSSTATUS 0x200 > #define CSR_VSIE 0x204 > @@ -291,6 +307,27 @@ > #define CSR_MENVCFG 0x30A > #define CSR_MENVCFGH 0x31A > > +/* Machine state CSRs */ > +#define CSR_MSTATEEN0 0x30C > +#define CSR_MSTATEEN0H 0x31C > +#define CSR_MSTATEEN1 0x30D > +#define CSR_MSTATEEN1H 0x31D > +#define CSR_MSTATEEN2 0x30E > +#define CSR_MSTATEEN2H 0x31E > +#define CSR_MSTATEEN3 0x30F > +#define CSR_MSTATEEN3H 0x31F > + > +/* Common defines for all smstateen */ > +#define SMSTATEEN_MAX_COUNT 4 > +#define SMSTATEEN0_CS (1ULL << 0) > +#define SMSTATEEN0_FCSR (1ULL << 1) > +#define SMSTATEEN0_HSCONTXT (1ULL << 57) > +#define SMSTATEEN0_IMSIC (1ULL << 58) > +#define SMSTATEEN0_AIA (1ULL << 59) > +#define SMSTATEEN0_SVSLCT (1ULL << 60) > +#define SMSTATEEN0_HSENVCFG (1ULL << 62) > +#define SMSTATEEN_STATEEN (1ULL << 63) > + > /* Enhanced Physical Memory Protection (ePMP) */ > #define CSR_MSECCFG 0x747 > #define CSR_MSECCFGH 0x757 > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index b96db1b62b..bbfdd49abd 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -278,6 +278,72 @@ static RISCVException umode32(CPURISCVState *env, int csrno) > return umode(env, csrno); > } > > +static RISCVException mstateen(CPURISCVState *env, int csrno) > +{ > + CPUState *cs = env_cpu(env); > + RISCVCPU *cpu = RISCV_CPU(cs); > + > + if (!cpu->cfg.ext_smstateen) { > + return RISCV_EXCP_ILLEGAL_INST; > + } > + > + return any(env, csrno); > +} > + > +static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base) > +{ > + CPUState *cs = env_cpu(env); > + RISCVCPU *cpu = RISCV_CPU(cs); > + > + if (!cpu->cfg.ext_smstateen) { > + return RISCV_EXCP_ILLEGAL_INST; > + } > + > + if (env->priv < PRV_M) { > + if (!(env->mstateen[csrno - base] & SMSTATEEN_STATEEN)) { > + return RISCV_EXCP_ILLEGAL_INST; > + } > + } > + > + return hmode(env, csrno); > +} > + > +static RISCVException hstateen(CPURISCVState *env, int csrno) > +{ > + return hstateen_pred(env, csrno, CSR_HSTATEEN0); > +} > + > +static RISCVException hstateenh(CPURISCVState *env, int csrno) > +{ > + return hstateen_pred(env, csrno, CSR_HSTATEEN0H); > +} > + > +static RISCVException sstateen(CPURISCVState *env, int csrno) > +{ > + bool virt = riscv_cpu_virt_enabled(env); > + int index = csrno - CSR_SSTATEEN0; > + CPUState *cs = env_cpu(env); > + RISCVCPU *cpu = RISCV_CPU(cs); > + > + if (!cpu->cfg.ext_smstateen) { > + return RISCV_EXCP_ILLEGAL_INST; > + } > + > + if (env->priv < PRV_M) { > + if (!(env->mstateen[index] & SMSTATEEN_STATEEN)) { > + return RISCV_EXCP_ILLEGAL_INST; > + } > + > + if (virt) { > + if (!(env->hstateen[index] & SMSTATEEN_STATEEN)) { > + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; > + } > + } > + } > + > + return smode(env, csrno); > +} > + > /* Checks if PointerMasking registers could be accessed */ > static RISCVException pointer_masking(CPURISCVState *env, int csrno) > { > @@ -1856,6 +1922,263 @@ static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, > return RISCV_EXCP_NONE; > } > > +static inline void write_smstateen(CPURISCVState *env, uint64_t *reg, > + uint64_t wr_mask, uint64_t new_val) > +{ > + *reg = (*reg & ~wr_mask) | (new_val & wr_mask); > +} > + > +static RISCVException read_mstateen(CPURISCVState *env, int csrno, > + target_ulong *val) > +{ > + *val = env->mstateen[csrno - CSR_MSTATEEN0]; > + > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException write_mstateen(CPURISCVState *env, int csrno, > + uint64_t wr_mask, target_ulong new_val) > +{ > + uint64_t *reg; > + > + reg = &env->mstateen[csrno - CSR_MSTATEEN0]; > + write_smstateen(env, reg, wr_mask, new_val); > + > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException write_mstateen0(CPURISCVState *env, int csrno, > + target_ulong new_val) > +{ > + uint64_t wr_mask = SMSTATEEN_STATEEN; > + > + return write_mstateen(env, csrno, wr_mask, new_val); > +} > + > +static RISCVException write_mstateen1(CPURISCVState *env, int csrno, > + target_ulong new_val) > +{ > + return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val); > +} > + > +static RISCVException write_mstateen2(CPURISCVState *env, int csrno, > + target_ulong new_val) > +{ > + return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val); > +} > + > +static RISCVException write_mstateen3(CPURISCVState *env, int csrno, > + target_ulong new_val) > +{ > + return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val); > +} I still prefer mstateen1~3 to share the same read/write function currently. If you insist on distinguishing them, I think it's better to pass index directly than pass csrno to calculate index. The same to following similar cases. Otherwise, Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Regards, Weiwei Li > + > +static RISCVException read_mstateenh(CPURISCVState *env, int csrno, > + target_ulong *val) > +{ > + *val = env->mstateen[csrno - CSR_MSTATEEN0H] >> 32; > + > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException write_mstateenh(CPURISCVState *env, int csrno, > + uint64_t wr_mask, target_ulong new_val) > +{ > + uint64_t *reg, val; > + > + reg = &env->mstateen[csrno - CSR_MSTATEEN0H]; > + val = (uint64_t)new_val << 32; > + val |= *reg & 0xFFFFFFFF; > + write_smstateen(env, reg, wr_mask, val); > + > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException write_mstateen0h(CPURISCVState *env, int csrno, > + target_ulong new_val) > +{ > + uint64_t wr_mask = SMSTATEEN_STATEEN; > + > + return write_mstateenh(env, csrno, wr_mask, new_val); > +} > + > +static RISCVException write_mstateen1h(CPURISCVState *env, int csrno, > + target_ulong new_val) > +{ > + return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); > +} > + > +static RISCVException write_mstateen2h(CPURISCVState *env, int csrno, > + target_ulong new_val) > +{ > + return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); > +} > + > +static RISCVException write_mstateen3h(CPURISCVState *env, int csrno, > + target_ulong new_val) > +{ > + return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); > +} > + > +static RISCVException read_hstateen(CPURISCVState *env, int csrno, > + target_ulong *val) > +{ > + int index = csrno - CSR_HSTATEEN0; > + > + *val = env->hstateen[index] & env->mstateen[index]; > + > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException write_hstateen(CPURISCVState *env, int csrno, > + uint64_t mask, target_ulong new_val) > +{ > + int index = csrno - CSR_HSTATEEN0; > + uint64_t *reg, wr_mask; > + > + reg = &env->hstateen[index]; > + wr_mask = env->mstateen[index] & mask; > + write_smstateen(env, reg, wr_mask, new_val); > + > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException write_hstateen0(CPURISCVState *env, int csrno, > + target_ulong new_val) > +{ > + uint64_t wr_mask = SMSTATEEN_STATEEN; > + > + return write_hstateen(env, csrno, wr_mask, new_val); > +} > + > +static RISCVException write_hstateen1(CPURISCVState *env, int csrno, > + target_ulong new_val) > +{ > + return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val); > +} > + > +static RISCVException write_hstateen2(CPURISCVState *env, int csrno, > + target_ulong new_val) > +{ > + return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val); > +} > + > +static RISCVException write_hstateen3(CPURISCVState *env, int csrno, > + target_ulong new_val) > +{ > + return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val); > +} > + > +static RISCVException read_hstateenh(CPURISCVState *env, int csrno, > + target_ulong *val) > +{ > + int index = csrno - CSR_HSTATEEN0H; > + > + *val = (env->hstateen[index] >> 32) & (env->mstateen[index] >> 32); > + > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException write_hstateenh(CPURISCVState *env, int csrno, > + uint64_t mask, target_ulong new_val) > +{ > + int index = csrno - CSR_HSTATEEN0H; > + uint64_t *reg, wr_mask, val; > + > + reg = &env->hstateen[index]; > + val = (uint64_t)new_val << 32; > + val |= *reg & 0xFFFFFFFF; > + wr_mask = env->mstateen[index] & mask; > + write_smstateen(env, reg, wr_mask, val); > + > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException write_hstateen0h(CPURISCVState *env, int csrno, > + target_ulong new_val) > +{ > + uint64_t wr_mask = SMSTATEEN_STATEEN; > + > + return write_hstateenh(env, csrno, wr_mask, new_val); > +} > + > +static RISCVException write_hstateen1h(CPURISCVState *env, int csrno, > + target_ulong new_val) > +{ > + return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); > +} > + > +static RISCVException write_hstateen2h(CPURISCVState *env, int csrno, > + target_ulong new_val) > +{ > + return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); > +} > + > +static RISCVException write_hstateen3h(CPURISCVState *env, int csrno, > + target_ulong new_val) > +{ > + return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); > +} > + > +static RISCVException read_sstateen(CPURISCVState *env, int csrno, > + target_ulong *val) > +{ > + bool virt = riscv_cpu_virt_enabled(env); > + int index = csrno - CSR_SSTATEEN0; > + > + *val = env->sstateen[index] & env->mstateen[index]; > + if (virt) { > + *val &= env->hstateen[index]; > + } > + > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException write_sstateen(CPURISCVState *env, int csrno, > + uint64_t mask, target_ulong new_val) > +{ > + bool virt = riscv_cpu_virt_enabled(env); > + int index = csrno - CSR_SSTATEEN0; > + uint64_t wr_mask; > + uint64_t *reg; > + > + wr_mask = env->mstateen[index] & mask; > + if (virt) { > + wr_mask &= env->hstateen[index]; > + } > + > + reg = &env->sstateen[index]; > + write_smstateen(env, reg, wr_mask, new_val); > + > + return RISCV_EXCP_NONE; > +} > + > +static RISCVException write_sstateen0(CPURISCVState *env, int csrno, > + target_ulong new_val) > +{ > + uint64_t wr_mask = SMSTATEEN_STATEEN; > + > + return write_sstateen(env, csrno, wr_mask, new_val); > +} > + > +static RISCVException write_sstateen1(CPURISCVState *env, int csrno, > + target_ulong new_val) > +{ > + return write_sstateen(env, csrno, SMSTATEEN_STATEEN, new_val); > +} > + > +static RISCVException write_sstateen2(CPURISCVState *env, int csrno, > + target_ulong new_val) > +{ > + return write_sstateen(env, csrno, SMSTATEEN_STATEEN, new_val); > +} > + > +static RISCVException write_sstateen3(CPURISCVState *env, int csrno, > + target_ulong new_val) > +{ > + return write_sstateen(env, csrno, SMSTATEEN_STATEEN, new_val); > +} > + > static RISCVException rmw_mip64(CPURISCVState *env, int csrno, > uint64_t *ret_val, > uint64_t new_val, uint64_t wr_mask) > @@ -3732,6 +4055,56 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, write_henvcfgh, > .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + /* Smstateen extension CSRs */ > + [CSR_MSTATEEN0] = { "mstateen0", mstateen, read_mstateen, write_mstateen0, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_MSTATEEN0H] = { "mstateen0h", mstateen, read_mstateenh, > + write_mstateen0h, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_MSTATEEN1] = { "mstateen1", mstateen, read_mstateen, write_mstateen1, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_MSTATEEN1H] = { "mstateen1h", mstateen, read_mstateenh, > + write_mstateen1h, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_MSTATEEN2] = { "mstateen2", mstateen, read_mstateen, write_mstateen2, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_MSTATEEN2H] = { "mstateen2h", mstateen, read_mstateenh, > + write_mstateen2h, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_MSTATEEN3] = { "mstateen3", mstateen, read_mstateen, write_mstateen3, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_MSTATEEN3H] = { "mstateen3h", mstateen, read_mstateenh, > + write_mstateen3h, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HSTATEEN0] = { "hstateen0", hstateen, read_hstateen, write_hstateen0, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HSTATEEN0H] = { "hstateen0h", hstateenh, read_hstateenh, > + write_hstateen0h, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HSTATEEN1] = { "hstateen1", hstateen, read_hstateen, write_hstateen1, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HSTATEEN1H] = { "hstateen1h", hstateenh, read_hstateenh, > + write_hstateen1h, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HSTATEEN2] = { "hstateen2", hstateen, read_hstateen, write_hstateen2, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HSTATEEN2H] = { "hstateen2h", hstateenh, read_hstateenh, > + write_hstateen2h, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HSTATEEN3] = { "hstateen3", hstateen, read_hstateen, write_hstateen3, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_HSTATEEN3H] = { "hstateen3h", hstateenh, read_hstateenh, > + write_hstateen3h, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_SSTATEEN0] = { "sstateen0", sstateen, read_sstateen, write_sstateen0, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_SSTATEEN1] = { "sstateen1", sstateen, read_sstateen, write_sstateen1, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_SSTATEEN2] = { "sstateen2", sstateen, read_sstateen, write_sstateen2, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_SSTATEEN3] = { "sstateen3", sstateen, read_sstateen, write_sstateen3, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + > /* Supervisor Trap Setup */ > [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, > NULL, read_sstatus_i128 }, > diff --git a/target/riscv/machine.c b/target/riscv/machine.c > index 41098f6ad0..18e47f3764 100644 > --- a/target/riscv/machine.c > +++ b/target/riscv/machine.c > @@ -263,6 +263,26 @@ static int riscv_cpu_post_load(void *opaque, int version_id) > return 0; > } > > +static bool smstateen_needed(void *opaque) > +{ > + RISCVCPU *cpu = opaque; > + > + return cpu->cfg.ext_smstateen; > +} > + > +static const VMStateDescription vmstate_smstateen = { > + .name = "cpu/smtateen", > + .version_id = 1, > + .minimum_version_id = 1, > + .needed = smstateen_needed, > + .fields = (VMStateField[]) { > + VMSTATE_UINT64_ARRAY(env.mstateen, RISCVCPU, 4), > + VMSTATE_UINT64_ARRAY(env.hstateen, RISCVCPU, 4), > + VMSTATE_UINT64_ARRAY(env.sstateen, RISCVCPU, 4), > + VMSTATE_END_OF_LIST() > + } > +}; > + > static bool envcfg_needed(void *opaque) > { > RISCVCPU *cpu = opaque; > @@ -374,6 +394,7 @@ const VMStateDescription vmstate_riscv_cpu = { > &vmstate_kvmtimer, > &vmstate_envcfg, > &vmstate_debug, > + &vmstate_smstateen, > NULL > } > }; ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v9 1/4] target/riscv: Add smstateen support 2022-09-29 0:57 ` weiwei @ 2022-09-29 1:43 ` Alistair Francis 2022-10-01 13:57 ` mchitale 0 siblings, 1 reply; 11+ messages in thread From: Alistair Francis @ 2022-09-29 1:43 UTC (permalink / raw) To: weiwei Cc: Mayuresh Chitale, qemu-devel@nongnu.org Developers, open list:RISC-V, Alistair Francis On Thu, Sep 29, 2022 at 10:58 AM weiwei <liweiwei@iscas.ac.cn> wrote: > > > On 2022/9/19 14:29, Mayuresh Chitale wrote: > > Smstateen extension specifies a mechanism to close > > the potential covert channels that could cause security issues. > > > > This patch adds the CSRs defined in the specification and > > the corresponding predicates and read/write functions. > > > > Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> > > --- > > target/riscv/cpu.h | 4 + > > target/riscv/cpu_bits.h | 37 ++++ > > target/riscv/csr.c | 373 ++++++++++++++++++++++++++++++++++++++++ > > target/riscv/machine.c | 21 +++ > > 4 files changed, 435 insertions(+) > > > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index 06751e1e3e..e407abbf93 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -362,6 +362,9 @@ struct CPUArchState { > > > > /* CSRs for execution enviornment configuration */ > > uint64_t menvcfg; > > + uint64_t mstateen[SMSTATEEN_MAX_COUNT]; > > + uint64_t hstateen[SMSTATEEN_MAX_COUNT]; > > + uint64_t sstateen[SMSTATEEN_MAX_COUNT]; > > target_ulong senvcfg; > > uint64_t henvcfg; > > #endif > > @@ -437,6 +440,7 @@ struct RISCVCPUConfig { > > bool ext_ifencei; > > bool ext_icsr; > > bool ext_zihintpause; > > + bool ext_smstateen; > > bool ext_sstc; > > bool ext_svinval; > > bool ext_svnapot; > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > > index 7be12cac2e..9a3321e27c 100644 > > --- a/target/riscv/cpu_bits.h > > +++ b/target/riscv/cpu_bits.h > > @@ -199,6 +199,12 @@ > > /* Supervisor Configuration CSRs */ > > #define CSR_SENVCFG 0x10A > > > > +/* Supervisor state CSRs */ > > +#define CSR_SSTATEEN0 0x10C > > +#define CSR_SSTATEEN1 0x10D > > +#define CSR_SSTATEEN2 0x10E > > +#define CSR_SSTATEEN3 0x10F > > + > > /* Supervisor Trap Handling */ > > #define CSR_SSCRATCH 0x140 > > #define CSR_SEPC 0x141 > > @@ -246,6 +252,16 @@ > > #define CSR_HENVCFG 0x60A > > #define CSR_HENVCFGH 0x61A > > > > +/* Hypervisor state CSRs */ > > +#define CSR_HSTATEEN0 0x60C > > +#define CSR_HSTATEEN0H 0x61C > > +#define CSR_HSTATEEN1 0x60D > > +#define CSR_HSTATEEN1H 0x61D > > +#define CSR_HSTATEEN2 0x60E > > +#define CSR_HSTATEEN2H 0x61E > > +#define CSR_HSTATEEN3 0x60F > > +#define CSR_HSTATEEN3H 0x61F > > + > > /* Virtual CSRs */ > > #define CSR_VSSTATUS 0x200 > > #define CSR_VSIE 0x204 > > @@ -291,6 +307,27 @@ > > #define CSR_MENVCFG 0x30A > > #define CSR_MENVCFGH 0x31A > > > > +/* Machine state CSRs */ > > +#define CSR_MSTATEEN0 0x30C > > +#define CSR_MSTATEEN0H 0x31C > > +#define CSR_MSTATEEN1 0x30D > > +#define CSR_MSTATEEN1H 0x31D > > +#define CSR_MSTATEEN2 0x30E > > +#define CSR_MSTATEEN2H 0x31E > > +#define CSR_MSTATEEN3 0x30F > > +#define CSR_MSTATEEN3H 0x31F > > + > > +/* Common defines for all smstateen */ > > +#define SMSTATEEN_MAX_COUNT 4 > > +#define SMSTATEEN0_CS (1ULL << 0) > > +#define SMSTATEEN0_FCSR (1ULL << 1) > > +#define SMSTATEEN0_HSCONTXT (1ULL << 57) > > +#define SMSTATEEN0_IMSIC (1ULL << 58) > > +#define SMSTATEEN0_AIA (1ULL << 59) > > +#define SMSTATEEN0_SVSLCT (1ULL << 60) > > +#define SMSTATEEN0_HSENVCFG (1ULL << 62) > > +#define SMSTATEEN_STATEEN (1ULL << 63) > > + > > /* Enhanced Physical Memory Protection (ePMP) */ > > #define CSR_MSECCFG 0x747 > > #define CSR_MSECCFGH 0x757 > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > index b96db1b62b..bbfdd49abd 100644 > > --- a/target/riscv/csr.c > > +++ b/target/riscv/csr.c > > @@ -278,6 +278,72 @@ static RISCVException umode32(CPURISCVState *env, int csrno) > > return umode(env, csrno); > > } > > > > +static RISCVException mstateen(CPURISCVState *env, int csrno) > > +{ > > + CPUState *cs = env_cpu(env); > > + RISCVCPU *cpu = RISCV_CPU(cs); > > + > > + if (!cpu->cfg.ext_smstateen) { > > + return RISCV_EXCP_ILLEGAL_INST; > > + } > > + > > + return any(env, csrno); > > +} > > + > > +static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base) > > +{ > > + CPUState *cs = env_cpu(env); > > + RISCVCPU *cpu = RISCV_CPU(cs); > > + > > + if (!cpu->cfg.ext_smstateen) { > > + return RISCV_EXCP_ILLEGAL_INST; > > + } > > + > > + if (env->priv < PRV_M) { > > + if (!(env->mstateen[csrno - base] & SMSTATEEN_STATEEN)) { > > + return RISCV_EXCP_ILLEGAL_INST; > > + } > > + } > > + > > + return hmode(env, csrno); > > +} > > + > > +static RISCVException hstateen(CPURISCVState *env, int csrno) > > +{ > > + return hstateen_pred(env, csrno, CSR_HSTATEEN0); > > +} > > + > > +static RISCVException hstateenh(CPURISCVState *env, int csrno) > > +{ > > + return hstateen_pred(env, csrno, CSR_HSTATEEN0H); > > +} > > + > > +static RISCVException sstateen(CPURISCVState *env, int csrno) > > +{ > > + bool virt = riscv_cpu_virt_enabled(env); > > + int index = csrno - CSR_SSTATEEN0; > > + CPUState *cs = env_cpu(env); > > + RISCVCPU *cpu = RISCV_CPU(cs); > > + > > + if (!cpu->cfg.ext_smstateen) { > > + return RISCV_EXCP_ILLEGAL_INST; > > + } > > + > > + if (env->priv < PRV_M) { > > + if (!(env->mstateen[index] & SMSTATEEN_STATEEN)) { > > + return RISCV_EXCP_ILLEGAL_INST; > > + } > > + > > + if (virt) { > > + if (!(env->hstateen[index] & SMSTATEEN_STATEEN)) { > > + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; > > + } > > + } > > + } > > + > > + return smode(env, csrno); > > +} > > + > > /* Checks if PointerMasking registers could be accessed */ > > static RISCVException pointer_masking(CPURISCVState *env, int csrno) > > { > > @@ -1856,6 +1922,263 @@ static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, > > return RISCV_EXCP_NONE; > > } > > > > +static inline void write_smstateen(CPURISCVState *env, uint64_t *reg, > > + uint64_t wr_mask, uint64_t new_val) > > +{ > > + *reg = (*reg & ~wr_mask) | (new_val & wr_mask); > > +} > > + > > +static RISCVException read_mstateen(CPURISCVState *env, int csrno, > > + target_ulong *val) > > +{ > > + *val = env->mstateen[csrno - CSR_MSTATEEN0]; > > + > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException write_mstateen(CPURISCVState *env, int csrno, > > + uint64_t wr_mask, target_ulong new_val) > > +{ > > + uint64_t *reg; > > + > > + reg = &env->mstateen[csrno - CSR_MSTATEEN0]; > > + write_smstateen(env, reg, wr_mask, new_val); > > + > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException write_mstateen0(CPURISCVState *env, int csrno, > > + target_ulong new_val) > > +{ > > + uint64_t wr_mask = SMSTATEEN_STATEEN; > > + > > + return write_mstateen(env, csrno, wr_mask, new_val); > > +} > > + > > +static RISCVException write_mstateen1(CPURISCVState *env, int csrno, > > + target_ulong new_val) > > +{ > > + return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val); > > +} > > + > > +static RISCVException write_mstateen2(CPURISCVState *env, int csrno, > > + target_ulong new_val) > > +{ > > + return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val); > > +} > > + > > +static RISCVException write_mstateen3(CPURISCVState *env, int csrno, > > + target_ulong new_val) > > +{ > > + return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val); > > +} > > I still prefer mstateen1~3 to share the same read/write function currently. Yeah, I agree. This is a lot of functions that are all pretty much the same. I'm not sure we need the write_smstateen() function either, I'm not sure it really gets us a lot. Alistair > > If you insist on distinguishing them, I think it's better to pass index > directly than pass csrno to calculate index. > > The same to following similar cases. > > Otherwise, > > Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> > > Regards, > > Weiwei Li > > > + > > +static RISCVException read_mstateenh(CPURISCVState *env, int csrno, > > + target_ulong *val) > > +{ > > + *val = env->mstateen[csrno - CSR_MSTATEEN0H] >> 32; > > + > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException write_mstateenh(CPURISCVState *env, int csrno, > > + uint64_t wr_mask, target_ulong new_val) > > +{ > > + uint64_t *reg, val; > > + > > + reg = &env->mstateen[csrno - CSR_MSTATEEN0H]; > > + val = (uint64_t)new_val << 32; > > + val |= *reg & 0xFFFFFFFF; > > + write_smstateen(env, reg, wr_mask, val); > > + > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException write_mstateen0h(CPURISCVState *env, int csrno, > > + target_ulong new_val) > > +{ > > + uint64_t wr_mask = SMSTATEEN_STATEEN; > > + > > + return write_mstateenh(env, csrno, wr_mask, new_val); > > +} > > + > > +static RISCVException write_mstateen1h(CPURISCVState *env, int csrno, > > + target_ulong new_val) > > +{ > > + return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); > > +} > > + > > +static RISCVException write_mstateen2h(CPURISCVState *env, int csrno, > > + target_ulong new_val) > > +{ > > + return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); > > +} > > + > > +static RISCVException write_mstateen3h(CPURISCVState *env, int csrno, > > + target_ulong new_val) > > +{ > > + return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); > > +} > > + > > +static RISCVException read_hstateen(CPURISCVState *env, int csrno, > > + target_ulong *val) > > +{ > > + int index = csrno - CSR_HSTATEEN0; > > + > > + *val = env->hstateen[index] & env->mstateen[index]; > > + > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException write_hstateen(CPURISCVState *env, int csrno, > > + uint64_t mask, target_ulong new_val) > > +{ > > + int index = csrno - CSR_HSTATEEN0; > > + uint64_t *reg, wr_mask; > > + > > + reg = &env->hstateen[index]; > > + wr_mask = env->mstateen[index] & mask; > > + write_smstateen(env, reg, wr_mask, new_val); > > + > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException write_hstateen0(CPURISCVState *env, int csrno, > > + target_ulong new_val) > > +{ > > + uint64_t wr_mask = SMSTATEEN_STATEEN; > > + > > + return write_hstateen(env, csrno, wr_mask, new_val); > > +} > > + > > +static RISCVException write_hstateen1(CPURISCVState *env, int csrno, > > + target_ulong new_val) > > +{ > > + return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val); > > +} > > + > > +static RISCVException write_hstateen2(CPURISCVState *env, int csrno, > > + target_ulong new_val) > > +{ > > + return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val); > > +} > > + > > +static RISCVException write_hstateen3(CPURISCVState *env, int csrno, > > + target_ulong new_val) > > +{ > > + return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val); > > +} > > + > > +static RISCVException read_hstateenh(CPURISCVState *env, int csrno, > > + target_ulong *val) > > +{ > > + int index = csrno - CSR_HSTATEEN0H; > > + > > + *val = (env->hstateen[index] >> 32) & (env->mstateen[index] >> 32); > > + > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException write_hstateenh(CPURISCVState *env, int csrno, > > + uint64_t mask, target_ulong new_val) > > +{ > > + int index = csrno - CSR_HSTATEEN0H; > > + uint64_t *reg, wr_mask, val; > > + > > + reg = &env->hstateen[index]; > > + val = (uint64_t)new_val << 32; > > + val |= *reg & 0xFFFFFFFF; > > + wr_mask = env->mstateen[index] & mask; > > + write_smstateen(env, reg, wr_mask, val); > > + > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException write_hstateen0h(CPURISCVState *env, int csrno, > > + target_ulong new_val) > > +{ > > + uint64_t wr_mask = SMSTATEEN_STATEEN; > > + > > + return write_hstateenh(env, csrno, wr_mask, new_val); > > +} > > + > > +static RISCVException write_hstateen1h(CPURISCVState *env, int csrno, > > + target_ulong new_val) > > +{ > > + return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); > > +} > > + > > +static RISCVException write_hstateen2h(CPURISCVState *env, int csrno, > > + target_ulong new_val) > > +{ > > + return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); > > +} > > + > > +static RISCVException write_hstateen3h(CPURISCVState *env, int csrno, > > + target_ulong new_val) > > +{ > > + return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val); > > +} > > + > > +static RISCVException read_sstateen(CPURISCVState *env, int csrno, > > + target_ulong *val) > > +{ > > + bool virt = riscv_cpu_virt_enabled(env); > > + int index = csrno - CSR_SSTATEEN0; > > + > > + *val = env->sstateen[index] & env->mstateen[index]; > > + if (virt) { > > + *val &= env->hstateen[index]; > > + } > > + > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException write_sstateen(CPURISCVState *env, int csrno, > > + uint64_t mask, target_ulong new_val) > > +{ > > + bool virt = riscv_cpu_virt_enabled(env); > > + int index = csrno - CSR_SSTATEEN0; > > + uint64_t wr_mask; > > + uint64_t *reg; > > + > > + wr_mask = env->mstateen[index] & mask; > > + if (virt) { > > + wr_mask &= env->hstateen[index]; > > + } > > + > > + reg = &env->sstateen[index]; > > + write_smstateen(env, reg, wr_mask, new_val); > > + > > + return RISCV_EXCP_NONE; > > +} > > + > > +static RISCVException write_sstateen0(CPURISCVState *env, int csrno, > > + target_ulong new_val) > > +{ > > + uint64_t wr_mask = SMSTATEEN_STATEEN; > > + > > + return write_sstateen(env, csrno, wr_mask, new_val); > > +} > > + > > +static RISCVException write_sstateen1(CPURISCVState *env, int csrno, > > + target_ulong new_val) > > +{ > > + return write_sstateen(env, csrno, SMSTATEEN_STATEEN, new_val); > > +} > > + > > +static RISCVException write_sstateen2(CPURISCVState *env, int csrno, > > + target_ulong new_val) > > +{ > > + return write_sstateen(env, csrno, SMSTATEEN_STATEEN, new_val); > > +} > > + > > +static RISCVException write_sstateen3(CPURISCVState *env, int csrno, > > + target_ulong new_val) > > +{ > > + return write_sstateen(env, csrno, SMSTATEEN_STATEEN, new_val); > > +} > > + > > static RISCVException rmw_mip64(CPURISCVState *env, int csrno, > > uint64_t *ret_val, > > uint64_t new_val, uint64_t wr_mask) > > @@ -3732,6 +4055,56 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > > [CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, write_henvcfgh, > > .min_priv_ver = PRIV_VERSION_1_12_0 }, > > > > + /* Smstateen extension CSRs */ > > + [CSR_MSTATEEN0] = { "mstateen0", mstateen, read_mstateen, write_mstateen0, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_MSTATEEN0H] = { "mstateen0h", mstateen, read_mstateenh, > > + write_mstateen0h, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_MSTATEEN1] = { "mstateen1", mstateen, read_mstateen, write_mstateen1, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_MSTATEEN1H] = { "mstateen1h", mstateen, read_mstateenh, > > + write_mstateen1h, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_MSTATEEN2] = { "mstateen2", mstateen, read_mstateen, write_mstateen2, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_MSTATEEN2H] = { "mstateen2h", mstateen, read_mstateenh, > > + write_mstateen2h, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_MSTATEEN3] = { "mstateen3", mstateen, read_mstateen, write_mstateen3, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_MSTATEEN3H] = { "mstateen3h", mstateen, read_mstateenh, > > + write_mstateen3h, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_HSTATEEN0] = { "hstateen0", hstateen, read_hstateen, write_hstateen0, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_HSTATEEN0H] = { "hstateen0h", hstateenh, read_hstateenh, > > + write_hstateen0h, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_HSTATEEN1] = { "hstateen1", hstateen, read_hstateen, write_hstateen1, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_HSTATEEN1H] = { "hstateen1h", hstateenh, read_hstateenh, > > + write_hstateen1h, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_HSTATEEN2] = { "hstateen2", hstateen, read_hstateen, write_hstateen2, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_HSTATEEN2H] = { "hstateen2h", hstateenh, read_hstateenh, > > + write_hstateen2h, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_HSTATEEN3] = { "hstateen3", hstateen, read_hstateen, write_hstateen3, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_HSTATEEN3H] = { "hstateen3h", hstateenh, read_hstateenh, > > + write_hstateen3h, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_SSTATEEN0] = { "sstateen0", sstateen, read_sstateen, write_sstateen0, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_SSTATEEN1] = { "sstateen1", sstateen, read_sstateen, write_sstateen1, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_SSTATEEN2] = { "sstateen2", sstateen, read_sstateen, write_sstateen2, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_SSTATEEN3] = { "sstateen3", sstateen, read_sstateen, write_sstateen3, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + > > /* Supervisor Trap Setup */ > > [CSR_SSTATUS] = { "sstatus", smode, read_sstatus, write_sstatus, > > NULL, read_sstatus_i128 }, > > diff --git a/target/riscv/machine.c b/target/riscv/machine.c > > index 41098f6ad0..18e47f3764 100644 > > --- a/target/riscv/machine.c > > +++ b/target/riscv/machine.c > > @@ -263,6 +263,26 @@ static int riscv_cpu_post_load(void *opaque, int version_id) > > return 0; > > } > > > > +static bool smstateen_needed(void *opaque) > > +{ > > + RISCVCPU *cpu = opaque; > > + > > + return cpu->cfg.ext_smstateen; > > +} > > + > > +static const VMStateDescription vmstate_smstateen = { > > + .name = "cpu/smtateen", > > + .version_id = 1, > > + .minimum_version_id = 1, > > + .needed = smstateen_needed, > > + .fields = (VMStateField[]) { > > + VMSTATE_UINT64_ARRAY(env.mstateen, RISCVCPU, 4), > > + VMSTATE_UINT64_ARRAY(env.hstateen, RISCVCPU, 4), > > + VMSTATE_UINT64_ARRAY(env.sstateen, RISCVCPU, 4), > > + VMSTATE_END_OF_LIST() > > + } > > +}; > > + > > static bool envcfg_needed(void *opaque) > > { > > RISCVCPU *cpu = opaque; > > @@ -374,6 +394,7 @@ const VMStateDescription vmstate_riscv_cpu = { > > &vmstate_kvmtimer, > > &vmstate_envcfg, > > &vmstate_debug, > > + &vmstate_smstateen, > > NULL > > } > > }; > > ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v9 1/4] target/riscv: Add smstateen support 2022-09-29 1:43 ` Alistair Francis @ 2022-10-01 13:57 ` mchitale 0 siblings, 0 replies; 11+ messages in thread From: mchitale @ 2022-10-01 13:57 UTC (permalink / raw) To: Alistair Francis, weiwei Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Alistair Francis On Thu, 2022-09-29 at 11:43 +1000, Alistair Francis wrote: > On Thu, Sep 29, 2022 at 10:58 AM weiwei <liweiwei@iscas.ac.cn> wrote: > > > > On 2022/9/19 14:29, Mayuresh Chitale wrote: > > > Smstateen extension specifies a mechanism to close > > > the potential covert channels that could cause security issues. > > > > > > This patch adds the CSRs defined in the specification and > > > the corresponding predicates and read/write functions. > > > > > > Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> > > > --- > > > target/riscv/cpu.h | 4 + > > > target/riscv/cpu_bits.h | 37 ++++ > > > target/riscv/csr.c | 373 > > > ++++++++++++++++++++++++++++++++++++++++ > > > target/riscv/machine.c | 21 +++ > > > 4 files changed, 435 insertions(+) > > > > > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > > index 06751e1e3e..e407abbf93 100644 > > > --- a/target/riscv/cpu.h > > > +++ b/target/riscv/cpu.h > > > @@ -362,6 +362,9 @@ struct CPUArchState { > > > > > > /* CSRs for execution enviornment configuration */ > > > uint64_t menvcfg; > > > + uint64_t mstateen[SMSTATEEN_MAX_COUNT]; > > > + uint64_t hstateen[SMSTATEEN_MAX_COUNT]; > > > + uint64_t sstateen[SMSTATEEN_MAX_COUNT]; > > > target_ulong senvcfg; > > > uint64_t henvcfg; > > > #endif > > > @@ -437,6 +440,7 @@ struct RISCVCPUConfig { > > > bool ext_ifencei; > > > bool ext_icsr; > > > bool ext_zihintpause; > > > + bool ext_smstateen; > > > bool ext_sstc; > > > bool ext_svinval; > > > bool ext_svnapot; > > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > > > index 7be12cac2e..9a3321e27c 100644 > > > --- a/target/riscv/cpu_bits.h > > > +++ b/target/riscv/cpu_bits.h > > > @@ -199,6 +199,12 @@ > > > /* Supervisor Configuration CSRs */ > > > #define CSR_SENVCFG 0x10A > > > > > > +/* Supervisor state CSRs */ > > > +#define CSR_SSTATEEN0 0x10C > > > +#define CSR_SSTATEEN1 0x10D > > > +#define CSR_SSTATEEN2 0x10E > > > +#define CSR_SSTATEEN3 0x10F > > > + > > > /* Supervisor Trap Handling */ > > > #define CSR_SSCRATCH 0x140 > > > #define CSR_SEPC 0x141 > > > @@ -246,6 +252,16 @@ > > > #define CSR_HENVCFG 0x60A > > > #define CSR_HENVCFGH 0x61A > > > > > > +/* Hypervisor state CSRs */ > > > +#define CSR_HSTATEEN0 0x60C > > > +#define CSR_HSTATEEN0H 0x61C > > > +#define CSR_HSTATEEN1 0x60D > > > +#define CSR_HSTATEEN1H 0x61D > > > +#define CSR_HSTATEEN2 0x60E > > > +#define CSR_HSTATEEN2H 0x61E > > > +#define CSR_HSTATEEN3 0x60F > > > +#define CSR_HSTATEEN3H 0x61F > > > + > > > /* Virtual CSRs */ > > > #define CSR_VSSTATUS 0x200 > > > #define CSR_VSIE 0x204 > > > @@ -291,6 +307,27 @@ > > > #define CSR_MENVCFG 0x30A > > > #define CSR_MENVCFGH 0x31A > > > > > > +/* Machine state CSRs */ > > > +#define CSR_MSTATEEN0 0x30C > > > +#define CSR_MSTATEEN0H 0x31C > > > +#define CSR_MSTATEEN1 0x30D > > > +#define CSR_MSTATEEN1H 0x31D > > > +#define CSR_MSTATEEN2 0x30E > > > +#define CSR_MSTATEEN2H 0x31E > > > +#define CSR_MSTATEEN3 0x30F > > > +#define CSR_MSTATEEN3H 0x31F > > > + > > > +/* Common defines for all smstateen */ > > > +#define SMSTATEEN_MAX_COUNT 4 > > > +#define SMSTATEEN0_CS (1ULL << 0) > > > +#define SMSTATEEN0_FCSR (1ULL << 1) > > > +#define SMSTATEEN0_HSCONTXT (1ULL << 57) > > > +#define SMSTATEEN0_IMSIC (1ULL << 58) > > > +#define SMSTATEEN0_AIA (1ULL << 59) > > > +#define SMSTATEEN0_SVSLCT (1ULL << 60) > > > +#define SMSTATEEN0_HSENVCFG (1ULL << 62) > > > +#define SMSTATEEN_STATEEN (1ULL << 63) > > > + > > > /* Enhanced Physical Memory Protection (ePMP) */ > > > #define CSR_MSECCFG 0x747 > > > #define CSR_MSECCFGH 0x757 > > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > > index b96db1b62b..bbfdd49abd 100644 > > > --- a/target/riscv/csr.c > > > +++ b/target/riscv/csr.c > > > @@ -278,6 +278,72 @@ static RISCVException umode32(CPURISCVState > > > *env, int csrno) > > > return umode(env, csrno); > > > } > > > > > > +static RISCVException mstateen(CPURISCVState *env, int csrno) > > > +{ > > > + CPUState *cs = env_cpu(env); > > > + RISCVCPU *cpu = RISCV_CPU(cs); > > > + > > > + if (!cpu->cfg.ext_smstateen) { > > > + return RISCV_EXCP_ILLEGAL_INST; > > > + } > > > + > > > + return any(env, csrno); > > > +} > > > + > > > +static RISCVException hstateen_pred(CPURISCVState *env, int > > > csrno, int base) > > > +{ > > > + CPUState *cs = env_cpu(env); > > > + RISCVCPU *cpu = RISCV_CPU(cs); > > > + > > > + if (!cpu->cfg.ext_smstateen) { > > > + return RISCV_EXCP_ILLEGAL_INST; > > > + } > > > + > > > + if (env->priv < PRV_M) { > > > + if (!(env->mstateen[csrno - base] & SMSTATEEN_STATEEN)) > > > { > > > + return RISCV_EXCP_ILLEGAL_INST; > > > + } > > > + } > > > + > > > + return hmode(env, csrno); > > > +} > > > + > > > +static RISCVException hstateen(CPURISCVState *env, int csrno) > > > +{ > > > + return hstateen_pred(env, csrno, CSR_HSTATEEN0); > > > +} > > > + > > > +static RISCVException hstateenh(CPURISCVState *env, int csrno) > > > +{ > > > + return hstateen_pred(env, csrno, CSR_HSTATEEN0H); > > > +} > > > + > > > +static RISCVException sstateen(CPURISCVState *env, int csrno) > > > +{ > > > + bool virt = riscv_cpu_virt_enabled(env); > > > + int index = csrno - CSR_SSTATEEN0; > > > + CPUState *cs = env_cpu(env); > > > + RISCVCPU *cpu = RISCV_CPU(cs); > > > + > > > + if (!cpu->cfg.ext_smstateen) { > > > + return RISCV_EXCP_ILLEGAL_INST; > > > + } > > > + > > > + if (env->priv < PRV_M) { > > > + if (!(env->mstateen[index] & SMSTATEEN_STATEEN)) { > > > + return RISCV_EXCP_ILLEGAL_INST; > > > + } > > > + > > > + if (virt) { > > > + if (!(env->hstateen[index] & SMSTATEEN_STATEEN)) { > > > + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; > > > + } > > > + } > > > + } > > > + > > > + return smode(env, csrno); > > > +} > > > + > > > /* Checks if PointerMasking registers could be accessed */ > > > static RISCVException pointer_masking(CPURISCVState *env, int > > > csrno) > > > { > > > @@ -1856,6 +1922,263 @@ static RISCVException > > > write_henvcfgh(CPURISCVState *env, int csrno, > > > return RISCV_EXCP_NONE; > > > } > > > > > > +static inline void write_smstateen(CPURISCVState *env, uint64_t > > > *reg, > > > + uint64_t wr_mask, uint64_t > > > new_val) > > > +{ > > > + *reg = (*reg & ~wr_mask) | (new_val & wr_mask); > > > +} > > > + > > > +static RISCVException read_mstateen(CPURISCVState *env, int > > > csrno, > > > + target_ulong *val) > > > +{ > > > + *val = env->mstateen[csrno - CSR_MSTATEEN0]; > > > + > > > + return RISCV_EXCP_NONE; > > > +} > > > + > > > +static RISCVException write_mstateen(CPURISCVState *env, int > > > csrno, > > > + uint64_t wr_mask, > > > target_ulong new_val) > > > +{ > > > + uint64_t *reg; > > > + > > > + reg = &env->mstateen[csrno - CSR_MSTATEEN0]; > > > + write_smstateen(env, reg, wr_mask, new_val); > > > + > > > + return RISCV_EXCP_NONE; > > > +} > > > + > > > +static RISCVException write_mstateen0(CPURISCVState *env, int > > > csrno, > > > + target_ulong new_val) > > > +{ > > > + uint64_t wr_mask = SMSTATEEN_STATEEN; > > > + > > > + return write_mstateen(env, csrno, wr_mask, new_val); > > > +} > > > + > > > +static RISCVException write_mstateen1(CPURISCVState *env, int > > > csrno, > > > + target_ulong new_val) > > > +{ > > > + return write_mstateen(env, csrno, SMSTATEEN_STATEEN, > > > new_val); > > > +} > > > + > > > +static RISCVException write_mstateen2(CPURISCVState *env, int > > > csrno, > > > + target_ulong new_val) > > > +{ > > > + return write_mstateen(env, csrno, SMSTATEEN_STATEEN, > > > new_val); > > > +} > > > + > > > +static RISCVException write_mstateen3(CPURISCVState *env, int > > > csrno, > > > + target_ulong new_val) > > > +{ > > > + return write_mstateen(env, csrno, SMSTATEEN_STATEEN, > > > new_val); > > > +} > > > > I still prefer mstateen1~3 to share the same read/write function > > currently. > > Yeah, I agree. This is a lot of functions that are all pretty much > the same. > > I'm not sure we need the write_smstateen() function either, I'm not > sure it really gets us a lot. > > Alistair Ok. I will send the updated patch. > > > If you insist on distinguishing them, I think it's better to pass > > index > > directly than pass csrno to calculate index. > > > > The same to following similar cases. > > > > Otherwise, > > > > Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> > > > > Regards, > > > > Weiwei Li > > > > > + > > > +static RISCVException read_mstateenh(CPURISCVState *env, int > > > csrno, > > > + target_ulong *val) > > > +{ > > > + *val = env->mstateen[csrno - CSR_MSTATEEN0H] >> 32; > > > + > > > + return RISCV_EXCP_NONE; > > > +} > > > + > > > +static RISCVException write_mstateenh(CPURISCVState *env, int > > > csrno, > > > + uint64_t wr_mask, > > > target_ulong new_val) > > > +{ > > > + uint64_t *reg, val; > > > + > > > + reg = &env->mstateen[csrno - CSR_MSTATEEN0H]; > > > + val = (uint64_t)new_val << 32; > > > + val |= *reg & 0xFFFFFFFF; > > > + write_smstateen(env, reg, wr_mask, val); > > > + > > > + return RISCV_EXCP_NONE; > > > +} > > > + > > > +static RISCVException write_mstateen0h(CPURISCVState *env, int > > > csrno, > > > + target_ulong new_val) > > > +{ > > > + uint64_t wr_mask = SMSTATEEN_STATEEN; > > > + > > > + return write_mstateenh(env, csrno, wr_mask, new_val); > > > +} > > > + > > > +static RISCVException write_mstateen1h(CPURISCVState *env, int > > > csrno, > > > + target_ulong new_val) > > > +{ > > > + return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, > > > new_val); > > > +} > > > + > > > +static RISCVException write_mstateen2h(CPURISCVState *env, int > > > csrno, > > > + target_ulong new_val) > > > +{ > > > + return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, > > > new_val); > > > +} > > > + > > > +static RISCVException write_mstateen3h(CPURISCVState *env, int > > > csrno, > > > + target_ulong new_val) > > > +{ > > > + return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, > > > new_val); > > > +} > > > + > > > +static RISCVException read_hstateen(CPURISCVState *env, int > > > csrno, > > > + target_ulong *val) > > > +{ > > > + int index = csrno - CSR_HSTATEEN0; > > > + > > > + *val = env->hstateen[index] & env->mstateen[index]; > > > + > > > + return RISCV_EXCP_NONE; > > > +} > > > + > > > +static RISCVException write_hstateen(CPURISCVState *env, int > > > csrno, > > > + uint64_t mask, target_ulong > > > new_val) > > > +{ > > > + int index = csrno - CSR_HSTATEEN0; > > > + uint64_t *reg, wr_mask; > > > + > > > + reg = &env->hstateen[index]; > > > + wr_mask = env->mstateen[index] & mask; > > > + write_smstateen(env, reg, wr_mask, new_val); > > > + > > > + return RISCV_EXCP_NONE; > > > +} > > > + > > > +static RISCVException write_hstateen0(CPURISCVState *env, int > > > csrno, > > > + target_ulong new_val) > > > +{ > > > + uint64_t wr_mask = SMSTATEEN_STATEEN; > > > + > > > + return write_hstateen(env, csrno, wr_mask, new_val); > > > +} > > > + > > > +static RISCVException write_hstateen1(CPURISCVState *env, int > > > csrno, > > > + target_ulong new_val) > > > +{ > > > + return write_hstateen(env, csrno, SMSTATEEN_STATEEN, > > > new_val); > > > +} > > > + > > > +static RISCVException write_hstateen2(CPURISCVState *env, int > > > csrno, > > > + target_ulong new_val) > > > +{ > > > + return write_hstateen(env, csrno, SMSTATEEN_STATEEN, > > > new_val); > > > +} > > > + > > > +static RISCVException write_hstateen3(CPURISCVState *env, int > > > csrno, > > > + target_ulong new_val) > > > +{ > > > + return write_hstateen(env, csrno, SMSTATEEN_STATEEN, > > > new_val); > > > +} > > > + > > > +static RISCVException read_hstateenh(CPURISCVState *env, int > > > csrno, > > > + target_ulong *val) > > > +{ > > > + int index = csrno - CSR_HSTATEEN0H; > > > + > > > + *val = (env->hstateen[index] >> 32) & (env->mstateen[index] > > > >> 32); > > > + > > > + return RISCV_EXCP_NONE; > > > +} > > > + > > > +static RISCVException write_hstateenh(CPURISCVState *env, int > > > csrno, > > > + uint64_t mask, > > > target_ulong new_val) > > > +{ > > > + int index = csrno - CSR_HSTATEEN0H; > > > + uint64_t *reg, wr_mask, val; > > > + > > > + reg = &env->hstateen[index]; > > > + val = (uint64_t)new_val << 32; > > > + val |= *reg & 0xFFFFFFFF; > > > + wr_mask = env->mstateen[index] & mask; > > > + write_smstateen(env, reg, wr_mask, val); > > > + > > > + return RISCV_EXCP_NONE; > > > +} > > > + > > > +static RISCVException write_hstateen0h(CPURISCVState *env, int > > > csrno, > > > + target_ulong new_val) > > > +{ > > > + uint64_t wr_mask = SMSTATEEN_STATEEN; > > > + > > > + return write_hstateenh(env, csrno, wr_mask, new_val); > > > +} > > > + > > > +static RISCVException write_hstateen1h(CPURISCVState *env, int > > > csrno, > > > + target_ulong new_val) > > > +{ > > > + return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, > > > new_val); > > > +} > > > + > > > +static RISCVException write_hstateen2h(CPURISCVState *env, int > > > csrno, > > > + target_ulong new_val) > > > +{ > > > + return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, > > > new_val); > > > +} > > > + > > > +static RISCVException write_hstateen3h(CPURISCVState *env, int > > > csrno, > > > + target_ulong new_val) > > > +{ > > > + return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, > > > new_val); > > > +} > > > + > > > +static RISCVException read_sstateen(CPURISCVState *env, int > > > csrno, > > > + target_ulong *val) > > > +{ > > > + bool virt = riscv_cpu_virt_enabled(env); > > > + int index = csrno - CSR_SSTATEEN0; > > > + > > > + *val = env->sstateen[index] & env->mstateen[index]; > > > + if (virt) { > > > + *val &= env->hstateen[index]; > > > + } > > > + > > > + return RISCV_EXCP_NONE; > > > +} > > > + > > > +static RISCVException write_sstateen(CPURISCVState *env, int > > > csrno, > > > + uint64_t mask, target_ulong > > > new_val) > > > +{ > > > + bool virt = riscv_cpu_virt_enabled(env); > > > + int index = csrno - CSR_SSTATEEN0; > > > + uint64_t wr_mask; > > > + uint64_t *reg; > > > + > > > + wr_mask = env->mstateen[index] & mask; > > > + if (virt) { > > > + wr_mask &= env->hstateen[index]; > > > + } > > > + > > > + reg = &env->sstateen[index]; > > > + write_smstateen(env, reg, wr_mask, new_val); > > > + > > > + return RISCV_EXCP_NONE; > > > +} > > > + > > > +static RISCVException write_sstateen0(CPURISCVState *env, int > > > csrno, > > > + target_ulong new_val) > > > +{ > > > + uint64_t wr_mask = SMSTATEEN_STATEEN; > > > + > > > + return write_sstateen(env, csrno, wr_mask, new_val); > > > +} > > > + > > > +static RISCVException write_sstateen1(CPURISCVState *env, int > > > csrno, > > > + target_ulong new_val) > > > +{ > > > + return write_sstateen(env, csrno, SMSTATEEN_STATEEN, > > > new_val); > > > +} > > > + > > > +static RISCVException write_sstateen2(CPURISCVState *env, int > > > csrno, > > > + target_ulong new_val) > > > +{ > > > + return write_sstateen(env, csrno, SMSTATEEN_STATEEN, > > > new_val); > > > +} > > > + > > > +static RISCVException write_sstateen3(CPURISCVState *env, int > > > csrno, > > > + target_ulong new_val) > > > +{ > > > + return write_sstateen(env, csrno, SMSTATEEN_STATEEN, > > > new_val); > > > +} > > > + > > > static RISCVException rmw_mip64(CPURISCVState *env, int csrno, > > > uint64_t *ret_val, > > > uint64_t new_val, uint64_t > > > wr_mask) > > > @@ -3732,6 +4055,56 @@ riscv_csr_operations > > > csr_ops[CSR_TABLE_SIZE] = { > > > [CSR_HENVCFGH] = { "henvcfgh", hmode32, read_henvcfgh, > > > write_henvcfgh, > > > .min_priv_ver = > > > PRIV_VERSION_1_12_0 }, > > > > > > + /* Smstateen extension CSRs */ > > > + [CSR_MSTATEEN0] = { "mstateen0", mstateen, read_mstateen, > > > write_mstateen0, > > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > > + [CSR_MSTATEEN0H] = { "mstateen0h", mstateen, read_mstateenh, > > > + write_mstateen0h, > > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > > + [CSR_MSTATEEN1] = { "mstateen1", mstateen, read_mstateen, > > > write_mstateen1, > > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > > + [CSR_MSTATEEN1H] = { "mstateen1h", mstateen, read_mstateenh, > > > + write_mstateen1h, > > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > > + [CSR_MSTATEEN2] = { "mstateen2", mstateen, read_mstateen, > > > write_mstateen2, > > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > > + [CSR_MSTATEEN2H] = { "mstateen2h", mstateen, read_mstateenh, > > > + write_mstateen2h, > > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > > + [CSR_MSTATEEN3] = { "mstateen3", mstateen, read_mstateen, > > > write_mstateen3, > > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > > + [CSR_MSTATEEN3H] = { "mstateen3h", mstateen, read_mstateenh, > > > + write_mstateen3h, > > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > > + [CSR_HSTATEEN0] = { "hstateen0", hstateen, read_hstateen, > > > write_hstateen0, > > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > > + [CSR_HSTATEEN0H] = { "hstateen0h", hstateenh, > > > read_hstateenh, > > > + write_hstateen0h, > > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > > + [CSR_HSTATEEN1] = { "hstateen1", hstateen, read_hstateen, > > > write_hstateen1, > > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > > + [CSR_HSTATEEN1H] = { "hstateen1h", hstateenh, > > > read_hstateenh, > > > + write_hstateen1h, > > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > > + [CSR_HSTATEEN2] = { "hstateen2", hstateen, read_hstateen, > > > write_hstateen2, > > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > > + [CSR_HSTATEEN2H] = { "hstateen2h", hstateenh, > > > read_hstateenh, > > > + write_hstateen2h, > > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > > + [CSR_HSTATEEN3] = { "hstateen3", hstateen, read_hstateen, > > > write_hstateen3, > > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > > + [CSR_HSTATEEN3H] = { "hstateen3h", hstateenh, > > > read_hstateenh, > > > + write_hstateen3h, > > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > > + [CSR_SSTATEEN0] = { "sstateen0", sstateen, read_sstateen, > > > write_sstateen0, > > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > > + [CSR_SSTATEEN1] = { "sstateen1", sstateen, read_sstateen, > > > write_sstateen1, > > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > > + [CSR_SSTATEEN2] = { "sstateen2", sstateen, read_sstateen, > > > write_sstateen2, > > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > > + [CSR_SSTATEEN3] = { "sstateen3", sstateen, read_sstateen, > > > write_sstateen3, > > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > > + > > > /* Supervisor Trap Setup */ > > > [CSR_SSTATUS] = { "sstatus", smode, > > > read_sstatus, write_sstatus, > > > NULL, read_sstatus_i128 > > > }, > > > diff --git a/target/riscv/machine.c b/target/riscv/machine.c > > > index 41098f6ad0..18e47f3764 100644 > > > --- a/target/riscv/machine.c > > > +++ b/target/riscv/machine.c > > > @@ -263,6 +263,26 @@ static int riscv_cpu_post_load(void *opaque, > > > int version_id) > > > return 0; > > > } > > > > > > +static bool smstateen_needed(void *opaque) > > > +{ > > > + RISCVCPU *cpu = opaque; > > > + > > > + return cpu->cfg.ext_smstateen; > > > +} > > > + > > > +static const VMStateDescription vmstate_smstateen = { > > > + .name = "cpu/smtateen", > > > + .version_id = 1, > > > + .minimum_version_id = 1, > > > + .needed = smstateen_needed, > > > + .fields = (VMStateField[]) { > > > + VMSTATE_UINT64_ARRAY(env.mstateen, RISCVCPU, 4), > > > + VMSTATE_UINT64_ARRAY(env.hstateen, RISCVCPU, 4), > > > + VMSTATE_UINT64_ARRAY(env.sstateen, RISCVCPU, 4), > > > + VMSTATE_END_OF_LIST() > > > + } > > > +}; > > > + > > > static bool envcfg_needed(void *opaque) > > > { > > > RISCVCPU *cpu = opaque; > > > @@ -374,6 +394,7 @@ const VMStateDescription vmstate_riscv_cpu = > > > { > > > &vmstate_kvmtimer, > > > &vmstate_envcfg, > > > &vmstate_debug, > > > + &vmstate_smstateen, > > > NULL > > > } > > > }; ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v9 2/4] target/riscv: smstateen check for h/s/envcfg 2022-09-19 6:29 [PATCH v9 0/4] RISC-V Smstateen support Mayuresh Chitale 2022-09-19 6:29 ` [PATCH v9 1/4] target/riscv: Add smstateen support Mayuresh Chitale @ 2022-09-19 6:29 ` Mayuresh Chitale 2022-09-19 6:29 ` [PATCH v9 3/4] target/riscv: smstateen check for fcsr Mayuresh Chitale 2022-09-19 6:29 ` [PATCH v9 4/4] target/riscv: smstateen knobs Mayuresh Chitale 3 siblings, 0 replies; 11+ messages in thread From: Mayuresh Chitale @ 2022-09-19 6:29 UTC (permalink / raw) To: qemu-devel, qemu-riscv; +Cc: Mayuresh Chitale, alistair.francis, Weiwei Li Accesses to henvcfg, henvcfgh and senvcfg are allowed only if the corresponding bit in mstateen0/hstateen0 is enabled. Otherwise an illegal instruction trap is generated. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> --- target/riscv/csr.c | 87 ++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 80 insertions(+), 7 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index bbfdd49abd..59d5aa74ee 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -41,6 +41,42 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) } /* Predicates */ +#if !defined(CONFIG_USER_ONLY) +static RISCVException smstateen_acc_ok(CPURISCVState *env, int index, + uint64_t bit) +{ + bool virt = riscv_cpu_virt_enabled(env); + CPUState *cs = env_cpu(env); + RISCVCPU *cpu = RISCV_CPU(cs); + + if (env->priv == PRV_M || !cpu->cfg.ext_smstateen) { + return RISCV_EXCP_NONE; + } + + if (!(env->mstateen[index] & bit)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + if (virt) { + if (!(env->hstateen[index] & bit)) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + + if (env->priv == PRV_U && !(env->sstateen[index] & bit)) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + } + + if (env->priv == PRV_U && riscv_has_ext(env, RVS)) { + if (!(env->sstateen[index] & bit)) { + return RISCV_EXCP_ILLEGAL_INST; + } + } + + return RISCV_EXCP_NONE; +} +#endif + static RISCVException fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) @@ -1869,6 +1905,13 @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, static RISCVException read_senvcfg(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); + if (ret != RISCV_EXCP_NONE) { + return ret; + } + *val = env->senvcfg; return RISCV_EXCP_NONE; } @@ -1877,15 +1920,27 @@ static RISCVException write_senvcfg(CPURISCVState *env, int csrno, target_ulong val) { uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE; + RISCVException ret; - env->senvcfg = (env->senvcfg & ~mask) | (val & mask); + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); + if (ret != RISCV_EXCP_NONE) { + return ret; + } + env->senvcfg = (env->senvcfg & ~mask) | (val & mask); return RISCV_EXCP_NONE; } static RISCVException read_henvcfg(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); + if (ret != RISCV_EXCP_NONE) { + return ret; + } + *val = env->henvcfg; return RISCV_EXCP_NONE; } @@ -1894,6 +1949,12 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno, target_ulong val) { uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE; + RISCVException ret; + + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); + if (ret != RISCV_EXCP_NONE) { + return ret; + } if (riscv_cpu_mxl(env) == MXL_RV64) { mask |= HENVCFG_PBMTE | HENVCFG_STCE; @@ -1907,6 +1968,13 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno, static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); + if (ret != RISCV_EXCP_NONE) { + return ret; + } + *val = env->henvcfg >> 32; return RISCV_EXCP_NONE; } @@ -1916,9 +1984,14 @@ static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, { uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE; uint64_t valh = (uint64_t)val << 32; + RISCVException ret; - env->henvcfg = (env->henvcfg & ~mask) | (valh & mask); + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); + if (ret != RISCV_EXCP_NONE) { + return ret; + } + env->henvcfg = (env->henvcfg & ~mask) | (valh & mask); return RISCV_EXCP_NONE; } @@ -1950,7 +2023,7 @@ static RISCVException write_mstateen(CPURISCVState *env, int csrno, static RISCVException write_mstateen0(CPURISCVState *env, int csrno, target_ulong new_val) { - uint64_t wr_mask = SMSTATEEN_STATEEN; + uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; return write_mstateen(env, csrno, wr_mask, new_val); } @@ -1997,7 +2070,7 @@ static RISCVException write_mstateenh(CPURISCVState *env, int csrno, static RISCVException write_mstateen0h(CPURISCVState *env, int csrno, target_ulong new_val) { - uint64_t wr_mask = SMSTATEEN_STATEEN; + uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; return write_mstateenh(env, csrno, wr_mask, new_val); } @@ -2046,7 +2119,7 @@ static RISCVException write_hstateen(CPURISCVState *env, int csrno, static RISCVException write_hstateen0(CPURISCVState *env, int csrno, target_ulong new_val) { - uint64_t wr_mask = SMSTATEEN_STATEEN; + uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; return write_hstateen(env, csrno, wr_mask, new_val); } @@ -2097,7 +2170,7 @@ static RISCVException write_hstateenh(CPURISCVState *env, int csrno, static RISCVException write_hstateen0h(CPURISCVState *env, int csrno, target_ulong new_val) { - uint64_t wr_mask = SMSTATEEN_STATEEN; + uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; return write_hstateenh(env, csrno, wr_mask, new_val); } @@ -2156,7 +2229,7 @@ static RISCVException write_sstateen(CPURISCVState *env, int csrno, static RISCVException write_sstateen0(CPURISCVState *env, int csrno, target_ulong new_val) { - uint64_t wr_mask = SMSTATEEN_STATEEN; + uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; return write_sstateen(env, csrno, wr_mask, new_val); } -- 2.25.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v9 3/4] target/riscv: smstateen check for fcsr 2022-09-19 6:29 [PATCH v9 0/4] RISC-V Smstateen support Mayuresh Chitale 2022-09-19 6:29 ` [PATCH v9 1/4] target/riscv: Add smstateen support Mayuresh Chitale 2022-09-19 6:29 ` [PATCH v9 2/4] target/riscv: smstateen check for h/s/envcfg Mayuresh Chitale @ 2022-09-19 6:29 ` Mayuresh Chitale 2022-09-29 1:09 ` weiwei 2022-09-19 6:29 ` [PATCH v9 4/4] target/riscv: smstateen knobs Mayuresh Chitale 3 siblings, 1 reply; 11+ messages in thread From: Mayuresh Chitale @ 2022-09-19 6:29 UTC (permalink / raw) To: qemu-devel, qemu-riscv; +Cc: Mayuresh Chitale, alistair.francis If smstateen is implemented and sstateen0.fcsr is clear then the floating point operations must return illegal instruction exception or virtual instruction trap, if relevant. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> --- target/riscv/csr.c | 23 +++++++++++++ target/riscv/insn_trans/trans_rvf.c.inc | 40 +++++++++++++++++++++-- target/riscv/insn_trans/trans_rvzfh.c.inc | 12 +++++++ 3 files changed, 72 insertions(+), 3 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 59d5aa74ee..edaecf53ce 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -84,6 +84,10 @@ static RISCVException fs(CPURISCVState *env, int csrno) !RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { return RISCV_EXCP_ILLEGAL_INST; } + + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { + return smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR); + } #endif return RISCV_EXCP_NONE; } @@ -2024,6 +2028,9 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno, target_ulong new_val) { uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; + if (!riscv_has_ext(env, RVF)) { + wr_mask |= SMSTATEEN0_FCSR; + } return write_mstateen(env, csrno, wr_mask, new_val); } @@ -2072,6 +2079,10 @@ static RISCVException write_mstateen0h(CPURISCVState *env, int csrno, { uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; + if (!riscv_has_ext(env, RVF)) { + wr_mask |= SMSTATEEN0_FCSR; + } + return write_mstateenh(env, csrno, wr_mask, new_val); } @@ -2121,6 +2132,10 @@ static RISCVException write_hstateen0(CPURISCVState *env, int csrno, { uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; + if (!riscv_has_ext(env, RVF)) { + wr_mask |= SMSTATEEN0_FCSR; + } + return write_hstateen(env, csrno, wr_mask, new_val); } @@ -2172,6 +2187,10 @@ static RISCVException write_hstateen0h(CPURISCVState *env, int csrno, { uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; + if (!riscv_has_ext(env, RVF)) { + wr_mask |= SMSTATEEN0_FCSR; + } + return write_hstateenh(env, csrno, wr_mask, new_val); } @@ -2231,6 +2250,10 @@ static RISCVException write_sstateen0(CPURISCVState *env, int csrno, { uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; + if (!riscv_has_ext(env, RVF)) { + wr_mask |= SMSTATEEN0_FCSR; + } + return write_sstateen(env, csrno, wr_mask, new_val); } diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc index a1d3eb52ad..ce8a0cc34b 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -24,9 +24,43 @@ return false; \ } while (0) -#define REQUIRE_ZFINX_OR_F(ctx) do {\ - if (!ctx->cfg_ptr->ext_zfinx) { \ - REQUIRE_EXT(ctx, RVF); \ +#ifndef CONFIG_USER_ONLY +static inline bool smstateen_check(DisasContext *ctx, int index) +{ + CPUState *cpu = ctx->cs; + CPURISCVState *env = cpu->env_ptr; + uint64_t stateen = env->mstateen[index]; + + if (!ctx->cfg_ptr->ext_smstateen || env->priv == PRV_M) { + return true; + } + + if (ctx->virt_enabled) { + stateen &= env->hstateen[index]; + } + + if (env->priv == PRV_U && has_ext(ctx, RVS)) { + stateen &= env->sstateen[index]; + } + + if (!(stateen & SMSTATEEN0_FCSR)) { + return false; + } + + return true; +} +#else +#define smstateen_check(ctx, index) (true) +#endif + +#define REQUIRE_ZFINX_OR_F(ctx) do { \ + if (!has_ext(ctx, RVF)) { \ + if (!ctx->cfg_ptr->ext_zfinx) { \ + return false; \ + } \ + if (!smstateen_check(ctx, 0)) { \ + return false; \ + } \ } \ } while (0) diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc index 5d07150cd0..44d962c920 100644 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -20,18 +20,27 @@ if (!ctx->cfg_ptr->ext_zfh) { \ return false; \ } \ + if (!smstateen_check(ctx, 0)) { \ + return false; \ + } \ } while (0) #define REQUIRE_ZHINX_OR_ZFH(ctx) do { \ if (!ctx->cfg_ptr->ext_zhinx && !ctx->cfg_ptr->ext_zfh) { \ return false; \ } \ + if (!smstateen_check(ctx, 0)) { \ + return false; \ + } \ } while (0) #define REQUIRE_ZFH_OR_ZFHMIN(ctx) do { \ if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin)) { \ return false; \ } \ + if (!smstateen_check(ctx, 0)) { \ + return false; \ + } \ } while (0) #define REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx) do { \ @@ -39,6 +48,9 @@ ctx->cfg_ptr->ext_zhinx || ctx->cfg_ptr->ext_zhinxmin)) { \ return false; \ } \ + if (!smstateen_check(ctx, 0)) { \ + return false; \ + } \ } while (0) static bool trans_flh(DisasContext *ctx, arg_flh *a) -- 2.25.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v9 3/4] target/riscv: smstateen check for fcsr 2022-09-19 6:29 ` [PATCH v9 3/4] target/riscv: smstateen check for fcsr Mayuresh Chitale @ 2022-09-29 1:09 ` weiwei 2022-10-01 13:58 ` mchitale 0 siblings, 1 reply; 11+ messages in thread From: weiwei @ 2022-09-29 1:09 UTC (permalink / raw) To: Mayuresh Chitale, qemu-devel, qemu-riscv; +Cc: alistair.francis, liweiwei On 2022/9/19 14:29, Mayuresh Chitale wrote: > If smstateen is implemented and sstateen0.fcsr is clear then the floating point > operations must return illegal instruction exception or virtual instruction > trap, if relevant. > > Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> > --- > target/riscv/csr.c | 23 +++++++++++++ > target/riscv/insn_trans/trans_rvf.c.inc | 40 +++++++++++++++++++++-- > target/riscv/insn_trans/trans_rvzfh.c.inc | 12 +++++++ > 3 files changed, 72 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 59d5aa74ee..edaecf53ce 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -84,6 +84,10 @@ static RISCVException fs(CPURISCVState *env, int csrno) > !RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { > return RISCV_EXCP_ILLEGAL_INST; > } > + > + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { > + return smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR); > + } > #endif > return RISCV_EXCP_NONE; > } > @@ -2024,6 +2028,9 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno, > target_ulong new_val) > { > uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > + if (!riscv_has_ext(env, RVF)) { > + wr_mask |= SMSTATEEN0_FCSR; > + } > > return write_mstateen(env, csrno, wr_mask, new_val); > } > @@ -2072,6 +2079,10 @@ static RISCVException write_mstateen0h(CPURISCVState *env, int csrno, > { > uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > > + if (!riscv_has_ext(env, RVF)) { > + wr_mask |= SMSTATEEN0_FCSR; > + } > + > return write_mstateenh(env, csrno, wr_mask, new_val); > } > > @@ -2121,6 +2132,10 @@ static RISCVException write_hstateen0(CPURISCVState *env, int csrno, > { > uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > > + if (!riscv_has_ext(env, RVF)) { > + wr_mask |= SMSTATEEN0_FCSR; > + } > + > return write_hstateen(env, csrno, wr_mask, new_val); > } > > @@ -2172,6 +2187,10 @@ static RISCVException write_hstateen0h(CPURISCVState *env, int csrno, > { > uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > > + if (!riscv_has_ext(env, RVF)) { > + wr_mask |= SMSTATEEN0_FCSR; > + } > + > return write_hstateenh(env, csrno, wr_mask, new_val); > } > > @@ -2231,6 +2250,10 @@ static RISCVException write_sstateen0(CPURISCVState *env, int csrno, > { > uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > > + if (!riscv_has_ext(env, RVF)) { > + wr_mask |= SMSTATEEN0_FCSR; > + } > + > return write_sstateen(env, csrno, wr_mask, new_val); > } > > diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc > index a1d3eb52ad..ce8a0cc34b 100644 > --- a/target/riscv/insn_trans/trans_rvf.c.inc > +++ b/target/riscv/insn_trans/trans_rvf.c.inc > @@ -24,9 +24,43 @@ > return false; \ > } while (0) > > -#define REQUIRE_ZFINX_OR_F(ctx) do {\ > - if (!ctx->cfg_ptr->ext_zfinx) { \ > - REQUIRE_EXT(ctx, RVF); \ > +#ifndef CONFIG_USER_ONLY > +static inline bool smstateen_check(DisasContext *ctx, int index) > +{ > + CPUState *cpu = ctx->cs; > + CPURISCVState *env = cpu->env_ptr; > + uint64_t stateen = env->mstateen[index]; > + > + if (!ctx->cfg_ptr->ext_smstateen || env->priv == PRV_M) { > + return true; > + } > + > + if (ctx->virt_enabled) { > + stateen &= env->hstateen[index]; > + } > + > + if (env->priv == PRV_U && has_ext(ctx, RVS)) { > + stateen &= env->sstateen[index]; > + } > + > + if (!(stateen & SMSTATEEN0_FCSR)) { > + return false; > + } > + > + return true; > +} > +#else > +#define smstateen_check(ctx, index) (true) > +#endif > + > +#define REQUIRE_ZFINX_OR_F(ctx) do { \ > + if (!has_ext(ctx, RVF)) { \ > + if (!ctx->cfg_ptr->ext_zfinx) { \ > + return false; \ > + } \ > + if (!smstateen_check(ctx, 0)) { \ > + return false; \ > + } \ > } \ > } while (0) I think the potential exception triggered by smstateen_check is not correct here: "return false" can only trigger illegal instruction exception. However, smstateen_check is for accessing fcsr CSR, It may trigger illegal or virtual instruction exception based on the privilege mode and Xstateen CSRs. Regards, Weiwei Li > > diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc > index 5d07150cd0..44d962c920 100644 > --- a/target/riscv/insn_trans/trans_rvzfh.c.inc > +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc > @@ -20,18 +20,27 @@ > if (!ctx->cfg_ptr->ext_zfh) { \ > return false; \ > } \ > + if (!smstateen_check(ctx, 0)) { \ > + return false; \ > + } \ > } while (0) > > #define REQUIRE_ZHINX_OR_ZFH(ctx) do { \ > if (!ctx->cfg_ptr->ext_zhinx && !ctx->cfg_ptr->ext_zfh) { \ > return false; \ > } \ > + if (!smstateen_check(ctx, 0)) { \ > + return false; \ > + } \ > } while (0) > > #define REQUIRE_ZFH_OR_ZFHMIN(ctx) do { \ > if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin)) { \ > return false; \ > } \ > + if (!smstateen_check(ctx, 0)) { \ > + return false; \ > + } \ > } while (0) > > #define REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx) do { \ > @@ -39,6 +48,9 @@ > ctx->cfg_ptr->ext_zhinx || ctx->cfg_ptr->ext_zhinxmin)) { \ > return false; \ > } \ > + if (!smstateen_check(ctx, 0)) { \ > + return false; \ > + } \ > } while (0) > > static bool trans_flh(DisasContext *ctx, arg_flh *a) ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v9 3/4] target/riscv: smstateen check for fcsr 2022-09-29 1:09 ` weiwei @ 2022-10-01 13:58 ` mchitale 0 siblings, 0 replies; 11+ messages in thread From: mchitale @ 2022-10-01 13:58 UTC (permalink / raw) To: weiwei, qemu-devel, qemu-riscv; +Cc: alistair.francis On Thu, 2022-09-29 at 09:09 +0800, weiwei wrote: > On 2022/9/19 14:29, Mayuresh Chitale wrote: > > If smstateen is implemented and sstateen0.fcsr is clear then the > > floating point > > operations must return illegal instruction exception or virtual > > instruction > > trap, if relevant. > > > > Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> > > --- > > target/riscv/csr.c | 23 +++++++++++++ > > target/riscv/insn_trans/trans_rvf.c.inc | 40 > > +++++++++++++++++++++-- > > target/riscv/insn_trans/trans_rvzfh.c.inc | 12 +++++++ > > 3 files changed, 72 insertions(+), 3 deletions(-) > > > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > index 59d5aa74ee..edaecf53ce 100644 > > --- a/target/riscv/csr.c > > +++ b/target/riscv/csr.c > > @@ -84,6 +84,10 @@ static RISCVException fs(CPURISCVState *env, int > > csrno) > > !RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { > > return RISCV_EXCP_ILLEGAL_INST; > > } > > + > > + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { > > + return smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR); > > + } > > #endif > > return RISCV_EXCP_NONE; > > } > > @@ -2024,6 +2028,9 @@ static RISCVException > > write_mstateen0(CPURISCVState *env, int csrno, > > target_ulong new_val) > > { > > uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > > + if (!riscv_has_ext(env, RVF)) { > > + wr_mask |= SMSTATEEN0_FCSR; > > + } > > > > return write_mstateen(env, csrno, wr_mask, new_val); > > } > > @@ -2072,6 +2079,10 @@ static RISCVException > > write_mstateen0h(CPURISCVState *env, int csrno, > > { > > uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > > > > + if (!riscv_has_ext(env, RVF)) { > > + wr_mask |= SMSTATEEN0_FCSR; > > + } > > + > > return write_mstateenh(env, csrno, wr_mask, new_val); > > } > > > > @@ -2121,6 +2132,10 @@ static RISCVException > > write_hstateen0(CPURISCVState *env, int csrno, > > { > > uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > > > > + if (!riscv_has_ext(env, RVF)) { > > + wr_mask |= SMSTATEEN0_FCSR; > > + } > > + > > return write_hstateen(env, csrno, wr_mask, new_val); > > } > > > > @@ -2172,6 +2187,10 @@ static RISCVException > > write_hstateen0h(CPURISCVState *env, int csrno, > > { > > uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > > > > + if (!riscv_has_ext(env, RVF)) { > > + wr_mask |= SMSTATEEN0_FCSR; > > + } > > + > > return write_hstateenh(env, csrno, wr_mask, new_val); > > } > > > > @@ -2231,6 +2250,10 @@ static RISCVException > > write_sstateen0(CPURISCVState *env, int csrno, > > { > > uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; > > > > + if (!riscv_has_ext(env, RVF)) { > > + wr_mask |= SMSTATEEN0_FCSR; > > + } > > + > > return write_sstateen(env, csrno, wr_mask, new_val); > > } > > > > diff --git a/target/riscv/insn_trans/trans_rvf.c.inc > > b/target/riscv/insn_trans/trans_rvf.c.inc > > index a1d3eb52ad..ce8a0cc34b 100644 > > --- a/target/riscv/insn_trans/trans_rvf.c.inc > > +++ b/target/riscv/insn_trans/trans_rvf.c.inc > > @@ -24,9 +24,43 @@ > > return false; \ > > } while (0) > > > > -#define REQUIRE_ZFINX_OR_F(ctx) do {\ > > - if (!ctx->cfg_ptr->ext_zfinx) { \ > > - REQUIRE_EXT(ctx, RVF); \ > > +#ifndef CONFIG_USER_ONLY > > +static inline bool smstateen_check(DisasContext *ctx, int index) > > +{ > > + CPUState *cpu = ctx->cs; > > + CPURISCVState *env = cpu->env_ptr; > > + uint64_t stateen = env->mstateen[index]; > > + > > + if (!ctx->cfg_ptr->ext_smstateen || env->priv == PRV_M) { > > + return true; > > + } > > + > > + if (ctx->virt_enabled) { > > + stateen &= env->hstateen[index]; > > + } > > + > > + if (env->priv == PRV_U && has_ext(ctx, RVS)) { > > + stateen &= env->sstateen[index]; > > + } > > + > > + if (!(stateen & SMSTATEEN0_FCSR)) { > > + return false; > > + } > > + > > + return true; > > +} > > +#else > > +#define smstateen_check(ctx, index) (true) > > +#endif > > + > > +#define REQUIRE_ZFINX_OR_F(ctx) do { \ > > + if (!has_ext(ctx, RVF)) { \ > > + if (!ctx->cfg_ptr->ext_zfinx) { \ > > + return false; \ > > + } \ > > + if (!smstateen_check(ctx, 0)) { \ > > + return false; \ > > + } \ > > } \ > > } while (0) > > I think the potential exception triggered by smstateen_check is not > correct here: > > "return false" can only trigger illegal instruction exception. > > However, smstateen_check is for accessing fcsr CSR, It may trigger > illegal or virtual instruction exception > > based on the privilege mode and Xstateen CSRs. > > Regards, > > Weiwei Li Ok. Need to check on how to do it. > > > > > diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc > > b/target/riscv/insn_trans/trans_rvzfh.c.inc > > index 5d07150cd0..44d962c920 100644 > > --- a/target/riscv/insn_trans/trans_rvzfh.c.inc > > +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc > > @@ -20,18 +20,27 @@ > > if (!ctx->cfg_ptr->ext_zfh) { \ > > return false; \ > > } \ > > + if (!smstateen_check(ctx, 0)) { \ > > + return false; \ > > + } \ > > } while (0) > > > > #define REQUIRE_ZHINX_OR_ZFH(ctx) do { \ > > if (!ctx->cfg_ptr->ext_zhinx && !ctx->cfg_ptr->ext_zfh) { \ > > return false; \ > > } \ > > + if (!smstateen_check(ctx, 0)) { \ > > + return false; \ > > + } \ > > } while (0) > > > > #define REQUIRE_ZFH_OR_ZFHMIN(ctx) do { \ > > if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin)) { \ > > return false; \ > > } \ > > + if (!smstateen_check(ctx, 0)) { \ > > + return false; \ > > + } \ > > } while (0) > > > > #define REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx) do { \ > > @@ -39,6 +48,9 @@ > > ctx->cfg_ptr->ext_zhinx || ctx->cfg_ptr->ext_zhinxmin)) > > { \ > > return false; \ > > } \ > > + if (!smstateen_check(ctx, 0)) { \ > > + return false; \ > > + } \ > > } while (0) > > > > static bool trans_flh(DisasContext *ctx, arg_flh *a) ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v9 4/4] target/riscv: smstateen knobs 2022-09-19 6:29 [PATCH v9 0/4] RISC-V Smstateen support Mayuresh Chitale ` (2 preceding siblings ...) 2022-09-19 6:29 ` [PATCH v9 3/4] target/riscv: smstateen check for fcsr Mayuresh Chitale @ 2022-09-19 6:29 ` Mayuresh Chitale 2022-09-29 1:44 ` Alistair Francis 3 siblings, 1 reply; 11+ messages in thread From: Mayuresh Chitale @ 2022-09-19 6:29 UTC (permalink / raw) To: qemu-devel, qemu-riscv; +Cc: Mayuresh Chitale, alistair.francis, Weiwei Li Add knobs to allow users to enable smstateen and also export it via the ISA extension string. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn> --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index aee14a239a..1252ca71b3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -102,6 +102,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), + ISA_EXT_DATA_ENTRY(smstateen, true, PRIV_VERSION_1_12_0, ext_smstateen), ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia), ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf), ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc), @@ -1021,6 +1022,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), + DEFINE_PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, false), DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), -- 2.25.1 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v9 4/4] target/riscv: smstateen knobs 2022-09-19 6:29 ` [PATCH v9 4/4] target/riscv: smstateen knobs Mayuresh Chitale @ 2022-09-29 1:44 ` Alistair Francis 0 siblings, 0 replies; 11+ messages in thread From: Alistair Francis @ 2022-09-29 1:44 UTC (permalink / raw) To: Mayuresh Chitale Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Alistair Francis, Weiwei Li On Mon, Sep 19, 2022 at 4:58 PM Mayuresh Chitale <mchitale@ventanamicro.com> wrote: > > Add knobs to allow users to enable smstateen and also export it via the > ISA extension string. > > Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> > Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index aee14a239a..1252ca71b3 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -102,6 +102,7 @@ static const struct isa_ext_data isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), > ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), > ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), > + ISA_EXT_DATA_ENTRY(smstateen, true, PRIV_VERSION_1_12_0, ext_smstateen), > ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia), > ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf), > ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc), > @@ -1021,6 +1022,7 @@ static Property riscv_cpu_extensions[] = { > DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), > DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), > > + DEFINE_PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, false), > DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), > DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), > DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), > -- > 2.25.1 > > ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2022-10-01 14:01 UTC | newest] Thread overview: 11+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-09-19 6:29 [PATCH v9 0/4] RISC-V Smstateen support Mayuresh Chitale 2022-09-19 6:29 ` [PATCH v9 1/4] target/riscv: Add smstateen support Mayuresh Chitale 2022-09-29 0:57 ` weiwei 2022-09-29 1:43 ` Alistair Francis 2022-10-01 13:57 ` mchitale 2022-09-19 6:29 ` [PATCH v9 2/4] target/riscv: smstateen check for h/s/envcfg Mayuresh Chitale 2022-09-19 6:29 ` [PATCH v9 3/4] target/riscv: smstateen check for fcsr Mayuresh Chitale 2022-09-29 1:09 ` weiwei 2022-10-01 13:58 ` mchitale 2022-09-19 6:29 ` [PATCH v9 4/4] target/riscv: smstateen knobs Mayuresh Chitale 2022-09-29 1:44 ` Alistair Francis
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