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Sun, 06 Apr 2025 16:26:22 -0700 (PDT) MIME-Version: 1.0 References: <20220106210108.138226-1-frederic.petrot@univ-grenoble-alpes.fr> <9ae32149-fe18-49d3-a689-60ee6752c20d@univ-grenoble-alpes.fr> In-Reply-To: <9ae32149-fe18-49d3-a689-60ee6752c20d@univ-grenoble-alpes.fr> From: Alistair Francis Date: Mon, 7 Apr 2025 09:25:56 +1000 X-Gm-Features: ATxdqUHbzAg4aR86tj9EmZeF9tNlmTI-51wnUVtaN9Sel8INEA3R6dgRpQWcKxE Message-ID: Subject: Re: [PATCH v8 00/18] Adding partial support for 128-bit riscv target To: =?UTF-8?B?RnLDqWTDqXJpYyBQw6l0cm90?= Cc: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , qemu-devel@nongnu.org, qemu-riscv@nongnu.org, bin.meng@windriver.com, richard.henderson@linaro.org, palmer@dabbelt.com, fabien.portas@grenoble-inp.org, alistair.francis@wdc.com, Pierrick Bouvier , Anton Johansson Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::a2d; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa2d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, Apr 7, 2025 at 4:24=E2=80=AFAM Fr=C3=A9d=C3=A9ric P=C3=A9trot wrote: > > Hi Alistair, Phil, > well, I'm trying to keep the thing alive, checking from time to time that > the current QEMU still runs the 128-bit tests that I have, and on which > I continue (slowly) to do stuffs. If it's being used then I don't see any issue keeping it Alistair > I hope this can stay upstream for experimental/research purposes, but the > 128-bit riscv community is, I follow you on that, scarce for now. > > So, your call. > Cheers, > Fr=C3=A9d=C3=A9ric > > Le 04/04/2025 =C3=A0 05:26, Alistair Francis a =C3=A9crit : > > On Sat, Mar 22, 2025 at 1:09=E2=80=AFAM Philippe Mathieu-Daud=C3=A9 > > wrote: > >> > >> Hi, > >> > >> On 6/1/22 22:00, Fr=C3=A9d=C3=A9ric P=C3=A9trot wrote: > >>> This series of patches provides partial 128-bit support for the riscv > >>> target architecture, namely RVI and RVM, with minimal csr support. > >> > >> > >>> Fr=C3=A9d=C3=A9ric P=C3=A9trot (18): > >>> exec/memop: Adding signedness to quad definitions > >>> exec/memop: Adding signed quad and octo defines > >>> qemu/int128: addition of div/rem 128-bit operations > >>> target/riscv: additional macros to check instruction support > >>> target/riscv: separation of bitwise logic and arithmetic helpers > >>> target/riscv: array for the 64 upper bits of 128-bit registers > >>> target/riscv: setup everything for rv64 to support rv128 executio= n > >> > >> > >> I see this series has been merged as commit afe33262585, with > >> 332dab68785b describing: > >> > >> This patch adds the support of the '-cpu rv128' option to > >> qemu-system-riscv64 so that we can indicate that we want to > >> run rv128 executables. > >> > >> Still, there is no support for 128-bit insns at that stage > >> so qemu fails miserably (as expected) if launched with this > >> option. > >> > >> Is this code tested? 3 years passed so I wonder about possible > >> code bitrot here. > > > > From memory at the time there was some momentum for RV128. So this was > > merged with the expectation that it would continue to improve. > > > > That doesn't seem to have happened, either software or spec wise though= . > > > >> > >> (I reached this code by looking at targets not supporting MTTCG). > > > > I'm happy to remove the CPU if it's blocking you, it's experimental so > > it doesn't need to be deprecated or anything fancy. > > > > Alistair > > > >> > >>> target/riscv: moving some insns close to similar insns > >>> target/riscv: accessors to registers upper part and 128-bit load/= store > >>> target/riscv: support for 128-bit bitwise instructions > >>> target/riscv: support for 128-bit U-type instructions > >>> target/riscv: support for 128-bit shift instructions > >>> target/riscv: support for 128-bit arithmetic instructions > >>> target/riscv: support for 128-bit M extension > >>> target/riscv: adding high part of some csrs > >>> target/riscv: helper functions to wrap calls to 128-bit csr insns > >>> target/riscv: modification of the trans_csrxx for 128-bit support > >>> target/riscv: actual functions to realize crs 128-bit insns > >> > >> > > -- > +------------------------------------------------------------------------= ---+ > | Fr=C3=A9d=C3=A9ric P=C3=A9trot, Pr. Grenoble INP= -UGA@Ensimag/TIMA | > | Mob/Pho: +33 6 74 57 99 65/+33 4 76 57 48 70 Ad augusta per angus= ta | > | http://tima.univ-grenoble-alpes.fr frederic.petrot@univ-grenoble-alpes.= fr | > +------------------------------------------------------------------------= ---+ >