Re: [PATCH v1 7/7] target/riscv: Expose sxl32 configuration in RISC-V CPU

[Alistair Francis <alistair23@gmail.com>]

On Mon, Oct 7, 2024 at 2:19 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>
> From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
>
> Enable with "-cpu rv64,sxl32=on".
> When sxl32 is enabled, RV64 can boot 32-bit Linux with
> 64-bit Opensbi while requiring to make minor modifications
> to the Linux kernel source code.
>
> How to patch linux:
> https://git
>
> Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
> ---
>  target/riscv/cpu.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 9dbbb1ca77..86984b7f8f 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2665,6 +2665,7 @@ static Property riscv_cpu_properties[] = {
>
>  #ifndef CONFIG_USER_ONLY
>      DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC),
> +    DEFINE_PROP_BOOL("sxl32", RISCVCPU, cfg.sxl32, false),

I don't think we should add this (see the cover letter), but if we did
it would need documentation

Alistair

>  #endif
>
>      DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),
> --
> 2.43.0
>
>