From: Alistair Francis <alistair23@gmail.com>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>
Cc: guoren@linux.alibaba.com,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
Bin Meng <bin.meng@windriver.com>,
Richard Henderson <richard.henderson@linaro.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>
Subject: Re: [PATCH v6 20/22] target/riscv: Adjust scalar reg in vector with XLEN
Date: Wed, 19 Jan 2022 13:30:54 +1000 [thread overview]
Message-ID: <CAKmqyKO5ghxvdqqkip-1UE7TKLycf5NKMKvt8hPGt1ZdwFfcsg@mail.gmail.com> (raw)
In-Reply-To: <20220113114004.286796-21-zhiwei_liu@c-sky.com>
On Thu, Jan 13, 2022 at 10:20 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> When sew <= 32bits, not need to extend scalar reg.
> When sew > 32bits, if xlen is less that sew, we should sign extend
> the scalar register, except explicitly specified by the spec.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 1c8086d3a6..b6502cdc7c 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -1201,7 +1201,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
> dest = tcg_temp_new_ptr();
> mask = tcg_temp_new_ptr();
> src2 = tcg_temp_new_ptr();
> - src1 = get_gpr(s, rs1, EXT_NONE);
> + src1 = get_gpr(s, rs1, EXT_SIGN);
>
> data = FIELD_DP32(data, VDATA, VM, vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> --
> 2.25.1
>
>
next prev parent reply other threads:[~2022-01-19 3:32 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-13 11:39 [PATCH v6 00/22] Support UXL filed in xstatus LIU Zhiwei
2022-01-13 11:39 ` [PATCH v6 01/22] target/riscv: Adjust pmpcfg access with mxl LIU Zhiwei
2022-01-19 3:20 ` Alistair Francis
2022-01-13 11:39 ` [PATCH v6 02/22] target/riscv: Don't save pc when exception return LIU Zhiwei
2022-01-13 11:39 ` [PATCH v6 03/22] target/riscv: Sign extend link reg for jal and jalr LIU Zhiwei
2022-01-19 3:21 ` Alistair Francis
2022-01-13 11:39 ` [PATCH v6 04/22] target/riscv: Sign extend pc for different XLEN LIU Zhiwei
2022-01-13 11:39 ` [PATCH v6 05/22] target/riscv: Create xl field in env LIU Zhiwei
2022-01-19 3:24 ` Alistair Francis
2022-01-19 3:36 ` LIU Zhiwei
2022-01-19 3:43 ` Alistair Francis
2022-01-13 11:39 ` [PATCH v6 06/22] target/riscv: Ignore the pc bits above XLEN LIU Zhiwei
2022-01-13 11:39 ` [PATCH v6 07/22] target/riscv: Extend pc for runtime pc write LIU Zhiwei
2022-01-13 11:39 ` [PATCH v6 08/22] target/riscv: Use gdb xml according to max mxlen LIU Zhiwei
2022-01-13 11:39 ` [PATCH v6 09/22] target/riscv: Relax debug check for pm write LIU Zhiwei
2022-01-13 11:39 ` [PATCH v6 10/22] target/riscv: Adjust csr write mask with XLEN LIU Zhiwei
2022-01-13 11:39 ` [PATCH v6 11/22] target/riscv: Create current pm fields in env LIU Zhiwei
2022-01-13 11:39 ` [PATCH v6 12/22] target/riscv: Alloc tcg global for cur_pm[mask|base] LIU Zhiwei
2022-01-13 11:39 ` [PATCH v6 13/22] target/riscv: Calculate address according to XLEN LIU Zhiwei
2022-01-13 11:39 ` [PATCH v6 14/22] target/riscv: Split pm_enabled into mask and base LIU Zhiwei
2022-01-13 11:39 ` [PATCH v6 15/22] target/riscv: Split out the vill from vtype LIU Zhiwei
2022-01-13 11:39 ` [PATCH v6 16/22] target/riscv: Adjust vsetvl according to XLEN LIU Zhiwei
2022-01-13 11:39 ` [PATCH v6 17/22] target/riscv: Remove VILL field in VTYPE LIU Zhiwei
2022-01-13 11:40 ` [PATCH v6 18/22] target/riscv: Fix check range for first fault only LIU Zhiwei
2022-01-13 11:40 ` [PATCH v6 19/22] target/riscv: Adjust vector address with mask LIU Zhiwei
2022-01-13 11:40 ` [PATCH v6 20/22] target/riscv: Adjust scalar reg in vector with XLEN LIU Zhiwei
2022-01-19 3:30 ` Alistair Francis [this message]
2022-01-13 11:40 ` [PATCH v6 21/22] target/riscv: Enable uxl field write LIU Zhiwei
2022-01-13 11:40 ` [PATCH v6 22/22] target/riscv: Relax UXL field for debugging LIU Zhiwei
2022-01-19 3:34 ` Alistair Francis
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