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Sun, 23 Feb 2025 19:33:19 -0800 (PST) MIME-Version: 1.0 References: <20241205133003.184581-1-dbarboza@ventanamicro.com> <20241205133003.184581-10-dbarboza@ventanamicro.com> In-Reply-To: <20241205133003.184581-10-dbarboza@ventanamicro.com> From: Alistair Francis Date: Mon, 24 Feb 2025 13:32:53 +1000 X-Gm-Features: AWEUYZmuXyTXpgXSz9y2RZnFTX5yuDE0PfYQkBjoAS7EOmTk6Su_xrgWx34t0fA Message-ID: Subject: Re: [PATCH for-10.0 09/11] hw/riscv/riscv-iommu.c: add RISCV_IOMMU_CAP_HPM cap To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Tomasz Jeznach Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::92f; envelope-from=alistair23@gmail.com; helo=mail-ua1-x92f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Dec 5, 2024 at 11:34=E2=80=AFPM Daniel Henrique Barboza wrote: > > From: Tomasz Jeznach > > Now that we have every piece in place we can advertise CAP_HTM to > software, allowing any HPM aware driver to make use of the counters. > > HPM is enabled/disabled via the 'hpm-counters' attribute. Default value > is 31, max value is also 31. Setting it to zero will disable HPM > support. > > Signed-off-by: Tomasz Jeznach > Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis Alistair > --- > hw/riscv/riscv-iommu.c | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c > index 83cd529844..7df40900b0 100644 > --- a/hw/riscv/riscv-iommu.c > +++ b/hw/riscv/riscv-iommu.c > @@ -2256,6 +2256,15 @@ static void riscv_iommu_realize(DeviceState *dev, = Error **errp) > RISCV_IOMMU_CAP_SV48X4 | RISCV_IOMMU_CAP_SV57X4; > } > > + if (s->hpm_cntrs > 0) { > + /* Clip number of HPM counters to maximum supported (31). */ > + if (s->hpm_cntrs > RISCV_IOMMU_IOCOUNT_NUM) { > + s->hpm_cntrs =3D RISCV_IOMMU_IOCOUNT_NUM; > + } > + /* Enable hardware performance monitor interface */ > + s->cap |=3D RISCV_IOMMU_CAP_HPM; > + } > + > /* Out-of-reset translation mode: OFF (DMA disabled) BARE (passthrou= gh) */ > s->ddtp =3D set_field(0, RISCV_IOMMU_DDTP_MODE, s->enable_off ? > RISCV_IOMMU_DDTP_MODE_OFF : RISCV_IOMMU_DDTP_MOD= E_BARE); > @@ -2303,6 +2312,18 @@ static void riscv_iommu_realize(DeviceState *dev, = Error **errp) > RISCV_IOMMU_TR_REQ_CTL_GO_BUSY); > } > > + /* If HPM registers are enabled. */ > + if (s->cap & RISCV_IOMMU_CAP_HPM) { > + /* +1 for cycle counter bit. */ > + stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_IOCOUNTINH], > + ~((2 << s->hpm_cntrs) - 1)); > + stq_le_p(&s->regs_ro[RISCV_IOMMU_REG_IOHPMCYCLES], 0); > + memset(&s->regs_ro[RISCV_IOMMU_REG_IOHPMCTR_BASE], > + 0x00, s->hpm_cntrs * 8); > + memset(&s->regs_ro[RISCV_IOMMU_REG_IOHPMEVT_BASE], > + 0x00, s->hpm_cntrs * 8); > + } > + > /* Memory region for downstream access, if specified. */ > if (s->target_mr) { > s->target_as =3D g_new0(AddressSpace, 1); > -- > 2.47.1 > >