From: Alistair Francis <alistair23@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <alistair.francis@wdc.com>,
QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PULL 22/23] hw/riscv: Use the CPU to determine if 32-bit
Date: Thu, 14 Jan 2021 17:20:55 -0800 [thread overview]
Message-ID: <CAKmqyKOAGcobcPzkTrNN5GS9VhJpfmCnuwsA8hAcazhQA2VhkA@mail.gmail.com> (raw)
In-Reply-To: <CAFEAcA-FF0SC-LSWUxwDdQ_vutYEB=1UMB1nua2BEQm+_E8SdA@mail.gmail.com>
On Sun, Jan 10, 2021 at 11:55 AM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Fri, 18 Dec 2020 at 06:01, Alistair Francis <alistair.francis@wdc.com> wrote:
> >
> > Instead of using string compares to determine if a RISC-V machine is
> > using 32-bit or 64-bit CPUs we can use the initalised CPUs. This avoids
> > us having to maintain a list of CPU names to compare against.
> >
> > This commit also fixes the name of the function to match the
> > riscv_cpu_is_32bit() function.
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> > Message-id: 8ab7614e5df93ab5267788b73dcd75f9f5615e82.1608142916.git.alistair.francis@wdc.com
>
> Hi; coverity points out a probably-unintentional inefficiency here
> (CID 1438099, CID 1438100, CID 1438101):
>
> > --- a/hw/riscv/boot.c
> > +++ b/hw/riscv/boot.c
> > @@ -33,28 +33,16 @@
> >
> > #include <libfdt.h>
> >
> > -bool riscv_is_32_bit(MachineState *machine)
> > +bool riscv_is_32bit(RISCVHartArrayState harts)
>
> The RISCVHartArrayState type is 824 bytes long. That's a very
> big type to be passing by value. You probably wanted to pass a
> pointer to it instead. Similarly for the arguments to
> riscv_calc_kernel_start_addr() and riscv_setup_rom_reset_vec().
Thanks Peter, I'll send a patch.
Alistair
>
> thanks
> -- PMM
next prev parent reply other threads:[~2021-01-15 1:24 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-18 6:00 [PULL 00/23] riscv-to-apply queue Alistair Francis
2020-12-18 6:00 ` [PULL 01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB Alistair Francis
2020-12-18 6:00 ` [PULL 02/23] hw/riscv: microchip_pfsoc: add QSPI NOR flash Alistair Francis
2020-12-18 6:00 ` [PULL 03/23] hw/core/register.c: Don't use '#' flag of printf format Alistair Francis
2020-12-18 6:00 ` [PULL 04/23] target/riscv: Fix the bug of HLVX/HLV/HSV Alistair Francis
2020-12-18 6:00 ` [PULL 05/23] target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR Alistair Francis
2020-12-18 6:00 ` [PULL 06/23] intc/ibex_plic: Clear interrupts that occur during claim process Alistair Francis
2020-12-18 6:00 ` [PULL 07/23] hw/riscv: Expand the is 32-bit check to support more CPUs Alistair Francis
2020-12-18 6:00 ` [PULL 08/23] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU Alistair Francis
2020-12-18 6:01 ` [PULL 09/23] riscv: spike: Remove target macro conditionals Alistair Francis
2020-12-18 6:01 ` [PULL 10/23] riscv: virt: " Alistair Francis
2020-12-18 6:01 ` [PULL 11/23] hw/riscv: boot: Remove compile time XLEN checks Alistair Francis
2020-12-18 6:01 ` [PULL 12/23] hw/riscv: virt: " Alistair Francis
2020-12-18 6:01 ` [PULL 13/23] hw/riscv: spike: " Alistair Francis
2020-12-18 6:01 ` [PULL 14/23] hw/riscv: sifive_u: " Alistair Francis
2020-12-18 6:01 ` [PULL 15/23] target/riscv: fpu_helper: Match function defs in HELPER macros Alistair Francis
2020-12-18 6:01 ` [PULL 16/23] target/riscv: Add a riscv_cpu_is_32bit() helper function Alistair Francis
2020-12-18 6:01 ` [PULL 17/23] target/riscv: Specify the XLEN for CPUs Alistair Francis
2020-12-18 6:01 ` [PULL 18/23] target/riscv: cpu: Remove compile time XLEN checks Alistair Francis
2020-12-18 6:01 ` [PULL 19/23] target/riscv: cpu_helper: " Alistair Francis
2020-12-18 6:01 ` [PULL 20/23] target/riscv: csr: " Alistair Francis
2020-12-18 6:01 ` [PULL 21/23] target/riscv: cpu: Set XLEN independently from target Alistair Francis
2020-12-18 6:01 ` [PULL 22/23] hw/riscv: Use the CPU to determine if 32-bit Alistair Francis
2021-01-10 19:55 ` Peter Maydell
2021-01-15 1:20 ` Alistair Francis [this message]
2020-12-18 6:01 ` [PULL 23/23] riscv/opentitan: Update the OpenTitan memory layout Alistair Francis
2020-12-18 13:36 ` [PULL 00/23] riscv-to-apply queue Peter Maydell
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