* [PATCH v4 0/6] Introduce svukte ISA extension
@ 2024-11-20 7:48 Fea.Wang
2024-11-20 7:48 ` [PATCH v4 1/6] target/riscv: Add svukte extension capability variable Fea.Wang
` (5 more replies)
0 siblings, 6 replies; 10+ messages in thread
From: Fea.Wang @ 2024-11-20 7:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Fea.Wang
The Svukte ISA extension has been approved for fast-track development.
https://lf-riscv.atlassian.net/browse/RVS-2977
And there are Linux patches for the Svukte that are under review.
https://lore.kernel.org/kvm/20240920-dev-maxh-svukte-rebase-v1-0-7864a88a62bd@sifive.com/T/#mf70fcb22cd2987ad268c0efee9b8583197d3cb4f
Svukte provides a means to make user-mode accesses to supervisor memory
raise page faults in constant time, mitigating attacks that attempt to
discover the supervisor software's address-space layout.
Refer to the draft of svukte extension from:
https://github.com/riscv/riscv-isa-manual/pull/1564
base-commit: 27652f9ca9d831c67dd447346c6ee953669255f0
[v4]
* Add a svukte extension check in RV32.
* Refine the code.
[v3]
* Fix some typos
* Refine code by separating a function into two dedicated functions.
* Follow the riscv,isa order
[v2]
* Refactor the code
[v1]
* Add svukte extension
Fea.Wang (6):
target/riscv: Add svukte extension capability variable
target/riscv: Support senvcfg[UKTE] bit when svukte extension is
enabled
target/riscv: Support hstatus[HUKTE] bit when svukte extension is
enabled
target/riscv: Check memory access to meet svukte rule
target/riscv: Expose svukte ISA extension
target/riscv: Check svukte is not enabled in RV32
target/riscv/cpu.c | 2 ++
target/riscv/cpu_bits.h | 2 ++
target/riscv/cpu_cfg.h | 1 +
target/riscv/cpu_helper.c | 55 ++++++++++++++++++++++++++++++++++++++
target/riscv/csr.c | 7 +++++
target/riscv/tcg/tcg-cpu.c | 5 ++++
6 files changed, 72 insertions(+)
--
2.34.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v4 1/6] target/riscv: Add svukte extension capability variable
2024-11-20 7:48 [PATCH v4 0/6] Introduce svukte ISA extension Fea.Wang
@ 2024-11-20 7:48 ` Fea.Wang
2024-11-20 7:48 ` [PATCH v4 2/6] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled Fea.Wang
` (4 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Fea.Wang @ 2024-11-20 7:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Fea.Wang, Frank Chang,
Jim Shu
Refer to the draft of svukte extension from:
https://github.com/riscv/riscv-isa-manual/pull/1564
Svukte provides a means to make user-mode accesses to supervisor memory
raise page faults in constant time, mitigating attacks that attempt to
discover the supervisor software's address-space layout.
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_cfg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 59d6fc445d..d8771ca641 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -84,6 +84,7 @@ struct RISCVCPUConfig {
bool ext_svnapot;
bool ext_svpbmt;
bool ext_svvptc;
+ bool ext_svukte;
bool ext_zdinx;
bool ext_zaamo;
bool ext_zacas;
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v4 2/6] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled
2024-11-20 7:48 [PATCH v4 0/6] Introduce svukte ISA extension Fea.Wang
2024-11-20 7:48 ` [PATCH v4 1/6] target/riscv: Add svukte extension capability variable Fea.Wang
@ 2024-11-20 7:48 ` Fea.Wang
2024-11-20 7:48 ` [PATCH v4 3/6] target/riscv: Support hstatus[HUKTE] " Fea.Wang
` (3 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Fea.Wang @ 2024-11-20 7:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Fea.Wang, Frank Chang,
Jim Shu
Svukte extension add UKTE bit, bit[8] in senvcfg CSR. The bit will be
supported when the svukte extension is enabled.
When senvcfg[UKTE] bit is set, the memory access from U-mode should do
the svukte check only except HLV/HLVX/HSV H-mode instructions which
depend on hstatus[HUKTE].
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 4 ++++
2 files changed, 5 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 385a2c67c2..4b9f899217 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -785,6 +785,7 @@ typedef enum RISCVException {
#define SENVCFG_CBIE MENVCFG_CBIE
#define SENVCFG_CBCFE MENVCFG_CBCFE
#define SENVCFG_CBZE MENVCFG_CBZE
+#define SENVCFG_UKTE BIT(8)
#define HENVCFG_FIOM MENVCFG_FIOM
#define HENVCFG_LPE MENVCFG_LPE
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9846770820..1936a6f32a 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -2453,6 +2453,10 @@ static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
mask |= SENVCFG_SSE;
}
+ if (env_archcpu(env)->cfg.ext_svukte) {
+ mask |= SENVCFG_UKTE;
+ }
+
env->senvcfg = (env->senvcfg & ~mask) | (val & mask);
return RISCV_EXCP_NONE;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v4 3/6] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled
2024-11-20 7:48 [PATCH v4 0/6] Introduce svukte ISA extension Fea.Wang
2024-11-20 7:48 ` [PATCH v4 1/6] target/riscv: Add svukte extension capability variable Fea.Wang
2024-11-20 7:48 ` [PATCH v4 2/6] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled Fea.Wang
@ 2024-11-20 7:48 ` Fea.Wang
2024-11-20 7:48 ` [PATCH v4 4/6] target/riscv: Check memory access to meet svukte rule Fea.Wang
` (2 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Fea.Wang @ 2024-11-20 7:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Fea.Wang, Frank Chang,
Jim Shu
Svukte extension add HUKTE bit, bit[24] in hstatus CSR. The written
value will be masked when the svukte extension is not enabled.
When hstatus[HUKTE] bit is set, HLV/HLVX/HSV work in the U-mode should
do svukte check.
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 4b9f899217..fe4e34c64a 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -604,6 +604,7 @@ typedef enum {
#define HSTATUS_VTVM 0x00100000
#define HSTATUS_VTW 0x00200000
#define HSTATUS_VTSR 0x00400000
+#define HSTATUS_HUKTE 0x01000000
#define HSTATUS_VSXL 0x300000000
#define HSTATUS32_WPRI 0xFF8FF87E
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 1936a6f32a..b6fa8ae53f 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3540,6 +3540,9 @@ static RISCVException read_hstatus(CPURISCVState *env, int csrno,
static RISCVException write_hstatus(CPURISCVState *env, int csrno,
target_ulong val)
{
+ if (!env_archcpu(env)->cfg.ext_svukte) {
+ val = val & (~HSTATUS_HUKTE);
+ }
env->hstatus = val;
if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) {
qemu_log_mask(LOG_UNIMP,
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v4 4/6] target/riscv: Check memory access to meet svukte rule
2024-11-20 7:48 [PATCH v4 0/6] Introduce svukte ISA extension Fea.Wang
` (2 preceding siblings ...)
2024-11-20 7:48 ` [PATCH v4 3/6] target/riscv: Support hstatus[HUKTE] " Fea.Wang
@ 2024-11-20 7:48 ` Fea.Wang
2024-11-22 4:58 ` Alistair Francis
2024-11-20 7:48 ` [PATCH v4 5/6] target/riscv: Expose svukte ISA extension Fea.Wang
2024-11-20 7:48 ` [PATCH v4 6/6] target/riscv: Check svukte is not enabled in RV32 Fea.Wang
5 siblings, 1 reply; 10+ messages in thread
From: Fea.Wang @ 2024-11-20 7:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Fea.Wang, Frank Chang,
Jim Shu
Follow the Svukte spec, do the memory access address checking
1. Include instruction fetches or explicit memory accesses
2. System run in effective privilege U or VU
3. Check senvcfg[UKTE] being set, or hstatus[HUKTE] being set if
instruction is HLV, HLVX, HSV and execute from U mode to VU mode
4. Depend on Sv39 and check virtual addresses bit[SXLEN-1]
5. Raises a page-fault exception corresponding to the original access
type.
Ref: https://github.com/riscv/riscv-isa-manual/pull/1564/files
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu_helper.c | 55 +++++++++++++++++++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 0a3ead69ea..edb106b8a0 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -857,6 +857,55 @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot, hwaddr addr,
return TRANSLATE_SUCCESS;
}
+/* Returns 'true' if a svukte address check is needed */
+static bool do_svukte_check(CPURISCVState *env, bool first_stage,
+ int mode, bool virt)
+{
+ /* Svukte extension depends on Sv39. */
+ if (!(env_archcpu(env)->cfg.ext_svukte ||
+ !first_stage ||
+ VM_1_10_SV39 != get_field(env->satp, SATP64_MODE))) {
+ return false;
+ }
+
+ /*
+ * Check hstatus.HUKTE if the effective mode is switched to VU-mode by
+ * executing HLV/HLVX/HSV in U-mode.
+ * For other cases, check senvcfg.UKTE.
+ */
+ if (env->priv == PRV_U && !env->virt_enabled && virt) {
+ if (!get_field(env->hstatus, HSTATUS_HUKTE)) {
+ return false;
+ }
+ } else if (!get_field(env->senvcfg, SENVCFG_UKTE)) {
+ return false;
+ }
+
+ /*
+ * Svukte extension is qualified only in U or VU-mode.
+ *
+ * Effective mode can be switched to U or VU-mode by:
+ * - M-mode + mstatus.MPRV=1 + mstatus.MPP=U-mode.
+ * - Execute HLV/HLVX/HSV from HS-mode + hstatus.SPVP=0.
+ * - U-mode.
+ * - VU-mode.
+ * - Execute HLV/HLVX/HSV from U-mode + hstatus.HU=1.
+ */
+ if (mode != PRV_U) {
+ return false;
+ }
+
+ return true;
+}
+
+static bool check_svukte_addr(CPURISCVState *env, vaddr addr)
+{
+ /* svukte extension excludes RV32 */
+ uint32_t sxlen = 32 * riscv_cpu_sxl(env);
+ uint64_t high_bit = addr & (1UL << (sxlen - 1));
+ return !high_bit;
+}
+
/*
* get_physical_address - get the physical address for this virtual address
*
@@ -894,6 +943,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
MemTxResult res;
MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
int mode = mmuidx_priv(mmu_idx);
+ bool virt = mmuidx_2stage(mmu_idx);
bool use_background = false;
hwaddr ppn;
int napot_bits = 0;
@@ -901,6 +951,11 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
bool is_sstack_idx = ((mmu_idx & MMU_IDX_SS_WRITE) == MMU_IDX_SS_WRITE);
bool sstack_page = false;
+ if (do_svukte_check(env, first_stage, mode, virt) &&
+ !check_svukte_addr(env, addr)) {
+ return TRANSLATE_FAIL;
+ }
+
/*
* Check if we should use the background registers for the two
* stage translation. We don't need to check if we actually need
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v4 5/6] target/riscv: Expose svukte ISA extension
2024-11-20 7:48 [PATCH v4 0/6] Introduce svukte ISA extension Fea.Wang
` (3 preceding siblings ...)
2024-11-20 7:48 ` [PATCH v4 4/6] target/riscv: Check memory access to meet svukte rule Fea.Wang
@ 2024-11-20 7:48 ` Fea.Wang
2024-11-20 7:48 ` [PATCH v4 6/6] target/riscv: Check svukte is not enabled in RV32 Fea.Wang
5 siblings, 0 replies; 10+ messages in thread
From: Fea.Wang @ 2024-11-20 7:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Fea.Wang, Frank Chang,
Jim Shu
Add "svukte" in the ISA string when svukte extension is enabled.
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f219f0c3b5..6d3e9d563d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -199,6 +199,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
+ ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte),
ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc),
ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
@@ -1595,6 +1596,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
/* These are experimental so mark with 'x-' */
const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
+ MULTI_EXT_CFG_BOOL("x-svukte", ext_svukte, false),
DEFINE_PROP_END_OF_LIST(),
};
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v4 6/6] target/riscv: Check svukte is not enabled in RV32
2024-11-20 7:48 [PATCH v4 0/6] Introduce svukte ISA extension Fea.Wang
` (4 preceding siblings ...)
2024-11-20 7:48 ` [PATCH v4 5/6] target/riscv: Expose svukte ISA extension Fea.Wang
@ 2024-11-20 7:48 ` Fea.Wang
2024-11-22 5:00 ` Alistair Francis
5 siblings, 1 reply; 10+ messages in thread
From: Fea.Wang @ 2024-11-20 7:48 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Fea.Wang
Based on the spec, svukte depends on SV39, so it should not be enabled
in RV32.
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
---
target/riscv/tcg/tcg-cpu.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index c62c221696..4273f1f472 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -652,6 +652,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
+ if (mcc->misa_mxl_max == MXL_RV32 && cpu->cfg.ext_svukte) {
+ error_setg(errp, "svukte is not supported by to RV32");
+ return;
+ }
+
/*
* Disable isa extensions based on priv spec after we
* validated and set everything we need.
--
2.34.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v4 4/6] target/riscv: Check memory access to meet svukte rule
2024-11-20 7:48 ` [PATCH v4 4/6] target/riscv: Check memory access to meet svukte rule Fea.Wang
@ 2024-11-22 4:58 ` Alistair Francis
0 siblings, 0 replies; 10+ messages in thread
From: Alistair Francis @ 2024-11-22 4:58 UTC (permalink / raw)
To: Fea.Wang
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei,
Frank Chang, Jim Shu
On Wed, Nov 20, 2024 at 5:48 PM Fea.Wang <fea.wang@sifive.com> wrote:
>
> Follow the Svukte spec, do the memory access address checking
>
> 1. Include instruction fetches or explicit memory accesses
> 2. System run in effective privilege U or VU
> 3. Check senvcfg[UKTE] being set, or hstatus[HUKTE] being set if
> instruction is HLV, HLVX, HSV and execute from U mode to VU mode
> 4. Depend on Sv39 and check virtual addresses bit[SXLEN-1]
> 5. Raises a page-fault exception corresponding to the original access
> type.
>
> Ref: https://github.com/riscv/riscv-isa-manual/pull/1564/files
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Signed-off-by: Fea.Wang <fea.wang@sifive.com>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Jim Shu <jim.shu@sifive.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu_helper.c | 55 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 55 insertions(+)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 0a3ead69ea..edb106b8a0 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -857,6 +857,55 @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot, hwaddr addr,
> return TRANSLATE_SUCCESS;
> }
>
> +/* Returns 'true' if a svukte address check is needed */
> +static bool do_svukte_check(CPURISCVState *env, bool first_stage,
> + int mode, bool virt)
> +{
> + /* Svukte extension depends on Sv39. */
> + if (!(env_archcpu(env)->cfg.ext_svukte ||
> + !first_stage ||
> + VM_1_10_SV39 != get_field(env->satp, SATP64_MODE))) {
> + return false;
> + }
> +
> + /*
> + * Check hstatus.HUKTE if the effective mode is switched to VU-mode by
> + * executing HLV/HLVX/HSV in U-mode.
> + * For other cases, check senvcfg.UKTE.
> + */
> + if (env->priv == PRV_U && !env->virt_enabled && virt) {
> + if (!get_field(env->hstatus, HSTATUS_HUKTE)) {
> + return false;
> + }
> + } else if (!get_field(env->senvcfg, SENVCFG_UKTE)) {
> + return false;
> + }
> +
> + /*
> + * Svukte extension is qualified only in U or VU-mode.
> + *
> + * Effective mode can be switched to U or VU-mode by:
> + * - M-mode + mstatus.MPRV=1 + mstatus.MPP=U-mode.
> + * - Execute HLV/HLVX/HSV from HS-mode + hstatus.SPVP=0.
> + * - U-mode.
> + * - VU-mode.
> + * - Execute HLV/HLVX/HSV from U-mode + hstatus.HU=1.
> + */
> + if (mode != PRV_U) {
> + return false;
> + }
> +
> + return true;
> +}
> +
> +static bool check_svukte_addr(CPURISCVState *env, vaddr addr)
> +{
> + /* svukte extension excludes RV32 */
> + uint32_t sxlen = 32 * riscv_cpu_sxl(env);
> + uint64_t high_bit = addr & (1UL << (sxlen - 1));
> + return !high_bit;
> +}
> +
> /*
> * get_physical_address - get the physical address for this virtual address
> *
> @@ -894,6 +943,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
> MemTxResult res;
> MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
> int mode = mmuidx_priv(mmu_idx);
> + bool virt = mmuidx_2stage(mmu_idx);
> bool use_background = false;
> hwaddr ppn;
> int napot_bits = 0;
> @@ -901,6 +951,11 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
> bool is_sstack_idx = ((mmu_idx & MMU_IDX_SS_WRITE) == MMU_IDX_SS_WRITE);
> bool sstack_page = false;
>
> + if (do_svukte_check(env, first_stage, mode, virt) &&
> + !check_svukte_addr(env, addr)) {
> + return TRANSLATE_FAIL;
> + }
> +
> /*
> * Check if we should use the background registers for the two
> * stage translation. We don't need to check if we actually need
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v4 6/6] target/riscv: Check svukte is not enabled in RV32
2024-11-20 7:48 ` [PATCH v4 6/6] target/riscv: Check svukte is not enabled in RV32 Fea.Wang
@ 2024-11-22 5:00 ` Alistair Francis
2024-11-25 8:36 ` Fea Wang
0 siblings, 1 reply; 10+ messages in thread
From: Alistair Francis @ 2024-11-22 5:00 UTC (permalink / raw)
To: Fea.Wang
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei
On Wed, Nov 20, 2024 at 5:47 PM Fea.Wang <fea.wang@sifive.com> wrote:
>
> Based on the spec, svukte depends on SV39, so it should not be enabled
> in RV32.
The spec explicitly says it doesn't support RV32.
>
> Signed-off-by: Fea.Wang <fea.wang@sifive.com>
> ---
> target/riscv/tcg/tcg-cpu.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index c62c221696..4273f1f472 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -652,6 +652,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
> return;
> }
>
> + if (mcc->misa_mxl_max == MXL_RV32 && cpu->cfg.ext_svukte) {
> + error_setg(errp, "svukte is not supported by to RV32");
"svukte is not supported for RV32"
Alistair
> + return;
> + }
> +
> /*
> * Disable isa extensions based on priv spec after we
> * validated and set everything we need.
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v4 6/6] target/riscv: Check svukte is not enabled in RV32
2024-11-22 5:00 ` Alistair Francis
@ 2024-11-25 8:36 ` Fea Wang
0 siblings, 0 replies; 10+ messages in thread
From: Fea Wang @ 2024-11-25 8:36 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel, qemu-riscv, Palmer Dabbelt, Alistair Francis,
Bin Meng, Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei
[-- Attachment #1: Type: text/plain, Size: 1250 bytes --]
OK, thank you.
I will refine it in the next patches.
On Fri, Nov 22, 2024 at 1:00 PM Alistair Francis <alistair23@gmail.com>
wrote:
> On Wed, Nov 20, 2024 at 5:47 PM Fea.Wang <fea.wang@sifive.com> wrote:
> >
> > Based on the spec, svukte depends on SV39, so it should not be enabled
> > in RV32.
>
> The spec explicitly says it doesn't support RV32.
>
> >
> > Signed-off-by: Fea.Wang <fea.wang@sifive.com>
> > ---
> > target/riscv/tcg/tcg-cpu.c | 5 +++++
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> > index c62c221696..4273f1f472 100644
> > --- a/target/riscv/tcg/tcg-cpu.c
> > +++ b/target/riscv/tcg/tcg-cpu.c
> > @@ -652,6 +652,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU
> *cpu, Error **errp)
> > return;
> > }
> >
> > + if (mcc->misa_mxl_max == MXL_RV32 && cpu->cfg.ext_svukte) {
> > + error_setg(errp, "svukte is not supported by to RV32");
>
> "svukte is not supported for RV32"
>
> Alistair
>
> > + return;
> > + }
> > +
> > /*
> > * Disable isa extensions based on priv spec after we
> > * validated and set everything we need.
> > --
> > 2.34.1
> >
> >
>
[-- Attachment #2: Type: text/html, Size: 1908 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2024-11-25 8:37 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-11-20 7:48 [PATCH v4 0/6] Introduce svukte ISA extension Fea.Wang
2024-11-20 7:48 ` [PATCH v4 1/6] target/riscv: Add svukte extension capability variable Fea.Wang
2024-11-20 7:48 ` [PATCH v4 2/6] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled Fea.Wang
2024-11-20 7:48 ` [PATCH v4 3/6] target/riscv: Support hstatus[HUKTE] " Fea.Wang
2024-11-20 7:48 ` [PATCH v4 4/6] target/riscv: Check memory access to meet svukte rule Fea.Wang
2024-11-22 4:58 ` Alistair Francis
2024-11-20 7:48 ` [PATCH v4 5/6] target/riscv: Expose svukte ISA extension Fea.Wang
2024-11-20 7:48 ` [PATCH v4 6/6] target/riscv: Check svukte is not enabled in RV32 Fea.Wang
2024-11-22 5:00 ` Alistair Francis
2024-11-25 8:36 ` Fea Wang
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