From: Alistair Francis <alistair23@gmail.com>
To: Mayuresh Chitale <mchitale@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com,
Daniel Barboza <dbarboza@ventanamicro.com>,
liweiwei@iscas.ac.cn,
Richard Henderson <richard.henderson@linaro.org>
Subject: Re: [PATCH v5 1/3] target/riscv: smstateen check for fcsr
Date: Fri, 26 May 2023 11:10:05 +1000 [thread overview]
Message-ID: <CAKmqyKOGuVo5iDPZ-PyJ0z7EVTo5yhFnqR=E4+qOT0Dsiz58ig@mail.gmail.com> (raw)
In-Reply-To: <20230518175058.2772506-2-mchitale@ventanamicro.com>
On Fri, May 19, 2023 at 3:51 AM Mayuresh Chitale
<mchitale@ventanamicro.com> wrote:
>
> Implement the s/h/mstateen.fcsr bit as defined in the smstateen spec
> and check for it when accessing the fcsr register and its fields.
>
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 4451bd1263..3f6b824bd2 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -82,6 +82,10 @@ static RISCVException fs(CPURISCVState *env, int csrno)
> !riscv_cpu_cfg(env)->ext_zfinx) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
> +
> + if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
> + return smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR);
> + }
> #endif
> return RISCV_EXCP_NONE;
> }
> @@ -2100,6 +2104,9 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
> target_ulong new_val)
> {
> uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
> + if (!riscv_has_ext(env, RVF)) {
> + wr_mask |= SMSTATEEN0_FCSR;
> + }
>
> return write_mstateen(env, csrno, wr_mask, new_val);
> }
> @@ -2173,6 +2180,10 @@ static RISCVException write_hstateen0(CPURISCVState *env, int csrno,
> {
> uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
>
> + if (!riscv_has_ext(env, RVF)) {
> + wr_mask |= SMSTATEEN0_FCSR;
> + }
> +
> return write_hstateen(env, csrno, wr_mask, new_val);
> }
>
> @@ -2259,6 +2270,10 @@ static RISCVException write_sstateen0(CPURISCVState *env, int csrno,
> {
> uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
>
> + if (!riscv_has_ext(env, RVF)) {
> + wr_mask |= SMSTATEEN0_FCSR;
> + }
> +
> return write_sstateen(env, csrno, wr_mask, new_val);
> }
>
> --
> 2.34.1
>
next prev parent reply other threads:[~2023-05-26 1:11 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-18 17:50 [PATCH v5 0/3] Smstateen FCSR Mayuresh Chitale
2023-05-18 17:50 ` [PATCH v5 1/3] target/riscv: smstateen check for fcsr Mayuresh Chitale
2023-05-26 1:10 ` Alistair Francis [this message]
2023-05-18 17:50 ` [PATCH v5 2/3] target/riscv: Reuse tb->flags.FS Mayuresh Chitale
2023-05-26 1:12 ` Alistair Francis
2023-05-18 17:50 ` [PATCH v5 3/3] target/riscv: smstateen knobs Mayuresh Chitale
2023-05-26 1:13 ` [PATCH v5 0/3] Smstateen FCSR Alistair Francis
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