Re: [PATCH 3/3] hw/riscv: Connect Shakti UART to Shakti platform

[Alistair Francis <alistair23@gmail.com>]

On Sun, Mar 14, 2021 at 5:11 AM Vijai Kumar K <vijai@behindbytes.com> wrote:
>
> Connect one shakti uart to the shakti_c machine.
>
> Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
> ---
>  hw/riscv/shakti_c.c         | 7 +++++++
>  include/hw/riscv/shakti_c.h | 2 ++
>  2 files changed, 9 insertions(+)
>
> diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
> index e96436a3bf..07cc42a380 100644
> --- a/hw/riscv/shakti_c.c
> +++ b/hw/riscv/shakti_c.c
> @@ -133,6 +133,12 @@ static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp)
>          shakti_c_memmap[SHAKTI_C_CLINT].size, 0, 1,
>          SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
>          SIFIVE_CLINT_TIMEBASE_FREQ, false);
> +    qdev_prop_set_chr(DEVICE(&(sss->uart)), "chardev", serial_hd(0));
> +    if (!sysbus_realize(SYS_BUS_DEVICE(&sss->uart), errp)) {
> +        return;
> +    }
> +    sysbus_mmio_map(SYS_BUS_DEVICE(&sss->uart), 0,
> +                    shakti_c_memmap[SHAKTI_C_UART].base);

Are there no interrupts?

Alistair

>      /* ROM */
>      memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom",
>                             shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal);
> @@ -151,6 +157,7 @@ static void shakti_c_soc_instance_init(Object *obj)
>      ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj);
>
>      object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY);
> +    object_initialize_child(obj, "uart", &sss->uart, TYPE_SHAKTI_UART);
>
>      /*
>       * CPU type is fixed and we are not supporting passing from commandline yet.
> diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h
> index 6c66a160f5..3abb080d3c 100644
> --- a/include/hw/riscv/shakti_c.h
> +++ b/include/hw/riscv/shakti_c.h
> @@ -21,6 +21,7 @@
>
>  #include "hw/riscv/riscv_hart.h"
>  #include "hw/boards.h"
> +#include "hw/char/shakti_uart.h"
>
>  #define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc"
>  #define RISCV_SHAKTI_SOC(obj) \
> @@ -33,6 +34,7 @@ typedef struct ShaktiCSoCState {
>      /*< public >*/
>      RISCVHartArrayState cpus;
>      DeviceState *plic;
> +    ShaktiUartState uart;
>      MemoryRegion rom;
>
>  } ShaktiCSoCState;
> --
> 2.25.1
>
>
>