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b=oU9IOkZTxINdcBDLBTe4HRb29DlWHR3sKUqhj95Pt+qGxHWbtdqsJY384Vb9uR6D2/ y4KfHXouUqkUDuUtgNIfzUUQJiruHRE5HtmpdVmG7+6m1MWs+ikgA/V/zDuE0BoS8Wga RXmt+Pxe5f5siHBzI4b9O64Sz5tFGauIAT6UAKDdzmgt5KAyT6kgBtOpUXicVNrrZNor vq407/FsuDaLbj/TILX2FwyaWhRxbsqn9NXMssE0enkS93faMKn6+PTR2D1sMGw127H8 +ZVcfpn2y2LREiCx7rWffp8lx5NHI93pxJanbqYkMsAYhM2xSowO/9JU+Swiraon6ar6 pj0g== X-Gm-Message-State: AOJu0YwQrb+r1Qc7yv6sqvg/7BNhjBVUHQnWShNX1dbml0R4qUAed4Hx qpuz3Ubqlw8yOtVBvYKInZiLM3O72zwRwHS+x6Y5cvqmfrI= X-Google-Smtp-Source: AGHT+IGlEPyklZ3Uu2JuEV3VLoFAyzd4Xi5Q9Lwc8mv8OU6WTnnJKDVptB5S0UJ1jYIeHuYeIIFn2ArV4hvm/mIyCjg= X-Received: by 2002:a67:fb99:0:b0:45d:ad5d:41b4 with SMTP id n25-20020a67fb99000000b0045dad5d41b4mr1116171vsr.26.1700619076169; Tue, 21 Nov 2023 18:11:16 -0800 (PST) MIME-Version: 1.0 References: <20231121071757.7178-1-ivan.klokov@syntacore.com> <20231121071757.7178-3-ivan.klokov@syntacore.com> In-Reply-To: <20231121071757.7178-3-ivan.klokov@syntacore.com> From: Alistair Francis Date: Wed, 22 Nov 2023 12:10:49 +1000 Message-ID: Subject: Re: [PATCH v2 2/2] target/riscv/cpu_helper.c: Fix mxr bit behavior To: Ivan Klokov Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::932; envelope-from=alistair23@gmail.com; helo=mail-ua1-x932.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Nov 21, 2023 at 6:53=E2=80=AFPM Ivan Klokov wrote: > > According to RISCV Specification sect 9.5 on two stage translation when > V=3D1 the vsstatus(mstatus in QEMU's terms) field MXR, which makes > execute-only pages readable, only overrides VS-stage page protection. > Setting MXR at HS-level(mstatus_hs), however, overrides both VS-stage > and G-stage execute-only permissions. > > The hypervisor extension changes the behavior of MXR\MPV\MPRV bits. > Due to RISCV Specification sect. 9.4.1 when MPRV=3D1, explicit memory > accesses are translated and protected, and endianness is applied, as > though the current virtualization mode were set to MPV and the current > nominal privilege mode were set to MPP. vsstatus.MXR makes readable > those pages marked executable at the VS translation stage. > > Fixes: 36a18664ba ("target/riscv: Implement second stage MMU") > > Signed-off-by: Ivan Klokov Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu_helper.c | 24 ++++++++++++++++++++---- > 1 file changed, 20 insertions(+), 4 deletions(-) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 9ff0952e46..e7e23b34f4 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -1032,13 +1032,29 @@ restart: > prot |=3D PAGE_WRITE; > } > if (pte & PTE_X) { > - bool mxr; > + bool mxr =3D false; > > - if (first_stage =3D=3D true) { > + /* > + * Use mstatus for first stage or for the second stage without > + * virt_enabled (MPRV+MPV) > + */ > + if (first_stage || !env->virt_enabled) { > mxr =3D get_field(env->mstatus, MSTATUS_MXR); > - } else { > - mxr =3D get_field(env->vsstatus, MSTATUS_MXR); > } > + > + /* MPRV+MPV case, check VSSTATUS */ > + if (first_stage && two_stage && !env->virt_enabled) { > + mxr |=3D get_field(env->vsstatus, MSTATUS_MXR); > + } > + > + /* > + * Setting MXR at HS-level overrides both VS-stage and G-stage > + * execute-only permissions > + */ > + if (env->virt_enabled) { > + mxr |=3D get_field(env->mstatus_hs, MSTATUS_MXR); > + } > + > if (mxr) { > prot |=3D PAGE_READ; > } > -- > 2.34.1 > >