* [PATCH 1/2] target/riscv: Add the implied rule for G extension
@ 2025-05-14 4:11 frank.chang
2025-05-14 4:11 ` [PATCH 2/2] target/riscv: Add standard B extension implied rule frank.chang
2025-05-15 11:11 ` [PATCH 1/2] target/riscv: Add the implied rule for G extension Daniel Henrique Barboza
0 siblings, 2 replies; 5+ messages in thread
From: frank.chang @ 2025-05-14 4:11 UTC (permalink / raw)
To: qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs,
Jim Shu, Frank Chang
From: Jim Shu <jim.shu@sifive.com>
Add the missing implied rule from G to imafd_zicsr_zifencei.
Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d92874baa0..27edd5af62 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2520,6 +2520,18 @@ static RISCVCPUImpliedExtsRule RVV_IMPLIED = {
},
};
+static RISCVCPUImpliedExtsRule RVG_IMPLIED = {
+ .is_misa = true,
+ .ext = RVG,
+ .implied_misa_exts = RVI | RVM | RVA | RVF | RVD,
+ .implied_multi_exts = {
+ CPU_CFG_OFFSET(ext_zicsr),
+ CPU_CFG_OFFSET(ext_zifencei),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
static RISCVCPUImpliedExtsRule ZCB_IMPLIED = {
.ext = CPU_CFG_OFFSET(ext_zcb),
.implied_multi_exts = {
@@ -2898,7 +2910,7 @@ static RISCVCPUImpliedExtsRule SSCTR_IMPLIED = {
RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = {
&RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
- &RVM_IMPLIED, &RVV_IMPLIED, NULL
+ &RVM_IMPLIED, &RVV_IMPLIED, &RVG_IMPLIED, NULL
};
RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
--
2.49.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 2/2] target/riscv: Add standard B extension implied rule
2025-05-14 4:11 [PATCH 1/2] target/riscv: Add the implied rule for G extension frank.chang
@ 2025-05-14 4:11 ` frank.chang
2025-05-15 11:12 ` Daniel Henrique Barboza
2025-05-19 0:21 ` Alistair Francis
2025-05-15 11:11 ` [PATCH 1/2] target/riscv: Add the implied rule for G extension Daniel Henrique Barboza
1 sibling, 2 replies; 5+ messages in thread
From: frank.chang @ 2025-05-14 4:11 UTC (permalink / raw)
To: qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs,
Frank Chang, Jerry Zhang Jian, Jim Shu
From: Frank Chang <frank.chang@sifive.com>
Add the missing implied rule for standard B extension.
Standard B extension implies Zba, Zbb, Zbs extensions.
RISC-V B spec: https://github.com/riscv/riscv-b
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
---
target/riscv/cpu.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 27edd5af62..f737b703da 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2532,6 +2532,17 @@ static RISCVCPUImpliedExtsRule RVG_IMPLIED = {
},
};
+static RISCVCPUImpliedExtsRule RVB_IMPLIED = {
+ .is_misa = true,
+ .ext = RVB,
+ .implied_multi_exts = {
+ CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb),
+ CPU_CFG_OFFSET(ext_zbs),
+
+ RISCV_IMPLIED_EXTS_RULE_END
+ },
+};
+
static RISCVCPUImpliedExtsRule ZCB_IMPLIED = {
.ext = CPU_CFG_OFFSET(ext_zcb),
.implied_multi_exts = {
@@ -2910,7 +2921,8 @@ static RISCVCPUImpliedExtsRule SSCTR_IMPLIED = {
RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = {
&RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
- &RVM_IMPLIED, &RVV_IMPLIED, &RVG_IMPLIED, NULL
+ &RVM_IMPLIED, &RVV_IMPLIED, &RVG_IMPLIED,
+ &RVB_IMPLIED, NULL
};
RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
--
2.49.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH 2/2] target/riscv: Add standard B extension implied rule
2025-05-14 4:11 ` [PATCH 2/2] target/riscv: Add standard B extension implied rule frank.chang
@ 2025-05-15 11:12 ` Daniel Henrique Barboza
2025-05-19 0:21 ` Alistair Francis
1 sibling, 0 replies; 5+ messages in thread
From: Daniel Henrique Barboza @ 2025-05-15 11:12 UTC (permalink / raw)
To: frank.chang, qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Weiwei Li, Liu Zhiwei,
open list:RISC-V TCG CPUs, Jerry Zhang Jian, Jim Shu
On 5/14/25 1:11 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> Add the missing implied rule for standard B extension.
> Standard B extension implies Zba, Zbb, Zbs extensions.
>
> RISC-V B spec: https://github.com/riscv/riscv-b
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
> Reviewed-by: Jim Shu <jim.shu@sifive.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/cpu.c | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 27edd5af62..f737b703da 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2532,6 +2532,17 @@ static RISCVCPUImpliedExtsRule RVG_IMPLIED = {
> },
> };
>
> +static RISCVCPUImpliedExtsRule RVB_IMPLIED = {
> + .is_misa = true,
> + .ext = RVB,
> + .implied_multi_exts = {
> + CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb),
> + CPU_CFG_OFFSET(ext_zbs),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> static RISCVCPUImpliedExtsRule ZCB_IMPLIED = {
> .ext = CPU_CFG_OFFSET(ext_zcb),
> .implied_multi_exts = {
> @@ -2910,7 +2921,8 @@ static RISCVCPUImpliedExtsRule SSCTR_IMPLIED = {
>
> RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = {
> &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
> - &RVM_IMPLIED, &RVV_IMPLIED, &RVG_IMPLIED, NULL
> + &RVM_IMPLIED, &RVV_IMPLIED, &RVG_IMPLIED,
> + &RVB_IMPLIED, NULL
> };
>
> RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH 2/2] target/riscv: Add standard B extension implied rule
2025-05-14 4:11 ` [PATCH 2/2] target/riscv: Add standard B extension implied rule frank.chang
2025-05-15 11:12 ` Daniel Henrique Barboza
@ 2025-05-19 0:21 ` Alistair Francis
1 sibling, 0 replies; 5+ messages in thread
From: Alistair Francis @ 2025-05-19 0:21 UTC (permalink / raw)
To: frank.chang
Cc: qemu-devel, Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs,
Jerry Zhang Jian, Jim Shu
On Wed, May 14, 2025 at 2:12 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Add the missing implied rule for standard B extension.
> Standard B extension implies Zba, Zbb, Zbs extensions.
>
> RISC-V B spec: https://github.com/riscv/riscv-b
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
> Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 27edd5af62..f737b703da 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2532,6 +2532,17 @@ static RISCVCPUImpliedExtsRule RVG_IMPLIED = {
> },
> };
>
> +static RISCVCPUImpliedExtsRule RVB_IMPLIED = {
> + .is_misa = true,
> + .ext = RVB,
> + .implied_multi_exts = {
> + CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb),
> + CPU_CFG_OFFSET(ext_zbs),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> static RISCVCPUImpliedExtsRule ZCB_IMPLIED = {
> .ext = CPU_CFG_OFFSET(ext_zcb),
> .implied_multi_exts = {
> @@ -2910,7 +2921,8 @@ static RISCVCPUImpliedExtsRule SSCTR_IMPLIED = {
>
> RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = {
> &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
> - &RVM_IMPLIED, &RVV_IMPLIED, &RVG_IMPLIED, NULL
> + &RVM_IMPLIED, &RVV_IMPLIED, &RVG_IMPLIED,
> + &RVB_IMPLIED, NULL
> };
>
> RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
> --
> 2.49.0
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] target/riscv: Add the implied rule for G extension
2025-05-14 4:11 [PATCH 1/2] target/riscv: Add the implied rule for G extension frank.chang
2025-05-14 4:11 ` [PATCH 2/2] target/riscv: Add standard B extension implied rule frank.chang
@ 2025-05-15 11:11 ` Daniel Henrique Barboza
1 sibling, 0 replies; 5+ messages in thread
From: Daniel Henrique Barboza @ 2025-05-15 11:11 UTC (permalink / raw)
To: frank.chang, qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Weiwei Li, Liu Zhiwei,
open list:RISC-V TCG CPUs, Jim Shu
On 5/14/25 1:11 AM, frank.chang@sifive.com wrote:
> From: Jim Shu <jim.shu@sifive.com>
>
> Add the missing implied rule from G to imafd_zicsr_zifencei.
>
> Signed-off-by: Jim Shu <jim.shu@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> ---
Patch LGTM. I believe this will deprecate everything we're doing in
riscv_cpu_validate_g() in tcg-cpu.c and we should remove it in this same
patch.
Thanks,
Daniel
> target/riscv/cpu.c | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d92874baa0..27edd5af62 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2520,6 +2520,18 @@ static RISCVCPUImpliedExtsRule RVV_IMPLIED = {
> },
> };
>
> +static RISCVCPUImpliedExtsRule RVG_IMPLIED = {
> + .is_misa = true,
> + .ext = RVG,
> + .implied_misa_exts = RVI | RVM | RVA | RVF | RVD,
> + .implied_multi_exts = {
> + CPU_CFG_OFFSET(ext_zicsr),
> + CPU_CFG_OFFSET(ext_zifencei),
> +
> + RISCV_IMPLIED_EXTS_RULE_END
> + },
> +};
> +
> static RISCVCPUImpliedExtsRule ZCB_IMPLIED = {
> .ext = CPU_CFG_OFFSET(ext_zcb),
> .implied_multi_exts = {
> @@ -2898,7 +2910,7 @@ static RISCVCPUImpliedExtsRule SSCTR_IMPLIED = {
>
> RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = {
> &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
> - &RVM_IMPLIED, &RVV_IMPLIED, NULL
> + &RVM_IMPLIED, &RVV_IMPLIED, &RVG_IMPLIED, NULL
> };
>
> RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2025-05-19 0:21 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-05-14 4:11 [PATCH 1/2] target/riscv: Add the implied rule for G extension frank.chang
2025-05-14 4:11 ` [PATCH 2/2] target/riscv: Add standard B extension implied rule frank.chang
2025-05-15 11:12 ` Daniel Henrique Barboza
2025-05-19 0:21 ` Alistair Francis
2025-05-15 11:11 ` [PATCH 1/2] target/riscv: Add the implied rule for G extension Daniel Henrique Barboza
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).