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* [PATCH] docs/system: riscv: Update description of CPU
@ 2022-02-08 13:07 Yu Li
  2022-02-10  1:28 ` Alistair Francis
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Yu Li @ 2022-02-08 13:07 UTC (permalink / raw)
  To: qemu-devel, qemu-riscv; +Cc: bmeng.cn, alistair.francis, liyu.yukiteru

Since the hypervisor extension been non experimental and enabled for
default CPU, the previous command is no longer available and the
option `x-h=true` or `h=true` is also no longer required.

Signed-off-by: Yu Li <liyu.yukiteru@bytedance.com>
---
  docs/system/riscv/virt.rst | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
index fa016584bf..08ce3c4177 100644
--- a/docs/system/riscv/virt.rst
+++ b/docs/system/riscv/virt.rst
@@ -23,9 +23,9 @@ The ``virt`` machine supports the following devices:
  * 1 generic PCIe host bridge
  * The fw_cfg device that allows a guest to obtain data from QEMU

-Note that the default CPU is a generic RV32GC/RV64GC. Optional extensions
-can be enabled via command line parameters, e.g.: ``-cpu rv64,x-h=true``
-enables the hypervisor extension for RV64.
+The hypervisor extension has been enabled for the default CPU, so virtual
+machines with hypervisor extension can simply be used without explicitly
+declaring.

  Hardware configuration information
  ----------------------------------
-- 
2.20.1


^ permalink raw reply related	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2022-03-03 20:58 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2022-02-08 13:07 [PATCH] docs/system: riscv: Update description of CPU Yu Li
2022-02-10  1:28 ` Alistair Francis
2022-02-10  3:10 ` Alistair Francis
2022-03-03 20:55 ` Palmer Dabbelt

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