From: Alistair Francis <alistair23@gmail.com>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: qemu-devel@nongnu.org
Subject: Re: [PATCH 07/27] target/riscv: introduce RISCVCPUDef
Date: Mon, 7 Apr 2025 09:21:19 +1000 [thread overview]
Message-ID: <CAKmqyKONiANs7KZchDjdmdjJtP6qMNiZSuoMB7Sz6n4Tdp2C-Q@mail.gmail.com> (raw)
In-Reply-To: <20250406070254.274797-8-pbonzini@redhat.com>
On Sun, Apr 6, 2025 at 5:03 PM Paolo Bonzini <pbonzini@redhat.com> wrote:
>
> Start putting all the CPU definitions in a struct. Later this will replace
> instance_init functions with declarative code, for now just remove the
> ugly cast of class_data.
>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 4 ++++
> target/riscv/cpu.c | 27 ++++++++++++++++++---------
> 2 files changed, 22 insertions(+), 9 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7e10c08a771..65c8d6855ec 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -541,6 +541,10 @@ struct ArchCPU {
> const GPtrArray *decoders;
> };
>
> +typedef struct RISCVCPUDef {
> + RISCVMXL misa_mxl_max; /* max mxl for this cpu */
> +} RISCVCPUDef;
> +
> /**
> * RISCVCPUClass:
> * @parent_realize: The parent class' realize handler.
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 9603f8985b3..3bd2bff1328 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -3082,8 +3082,9 @@ static void riscv_cpu_common_class_init(ObjectClass *c, void *data)
> static void riscv_cpu_class_init(ObjectClass *c, void *data)
> {
> RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
> + const RISCVCPUDef *def = data;
>
> - mcc->misa_mxl_max = (RISCVMXL)GPOINTER_TO_UINT(data);
> + mcc->misa_mxl_max = def->misa_mxl_max;
> riscv_cpu_validate_misa_mxl(mcc);
> }
>
> @@ -3179,40 +3180,48 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
> }
> #endif
>
> -#define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max, initfn) \
> +#define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max_, initfn) \
> { \
> .name = (type_name), \
> .parent = TYPE_RISCV_DYNAMIC_CPU, \
> .instance_init = (initfn), \
> .class_init = riscv_cpu_class_init, \
> - .class_data = GUINT_TO_POINTER(misa_mxl_max) \
> + .class_data = (void*) &((const RISCVCPUDef) { \
> + .misa_mxl_max = (misa_mxl_max_), \
> + }), \
> }
>
> -#define DEFINE_VENDOR_CPU(type_name, misa_mxl_max, initfn) \
> +#define DEFINE_VENDOR_CPU(type_name, misa_mxl_max_, initfn) \
> { \
> .name = (type_name), \
> .parent = TYPE_RISCV_VENDOR_CPU, \
> .instance_init = (initfn), \
> .class_init = riscv_cpu_class_init, \
> - .class_data = GUINT_TO_POINTER(misa_mxl_max) \
> + .class_data = (void*) &((const RISCVCPUDef) { \
> + .misa_mxl_max = (misa_mxl_max_), \
> + }), \
> }
>
> -#define DEFINE_BARE_CPU(type_name, misa_mxl_max, initfn) \
> +#define DEFINE_BARE_CPU(type_name, misa_mxl_max_, initfn) \
> { \
> .name = (type_name), \
> .parent = TYPE_RISCV_BARE_CPU, \
> .instance_init = (initfn), \
> .class_init = riscv_cpu_class_init, \
> - .class_data = GUINT_TO_POINTER(misa_mxl_max) \
> + .class_data = (void*) &((const RISCVCPUDef) { \
> + .misa_mxl_max = (misa_mxl_max_), \
> + }), \
> }
>
> -#define DEFINE_PROFILE_CPU(type_name, misa_mxl_max, initfn) \
> +#define DEFINE_PROFILE_CPU(type_name, misa_mxl_max_, initfn) \
> { \
> .name = (type_name), \
> .parent = TYPE_RISCV_BARE_CPU, \
> .instance_init = (initfn), \
> .class_init = riscv_cpu_class_init, \
> - .class_data = GUINT_TO_POINTER(misa_mxl_max) \
> + .class_data = (void*) &((const RISCVCPUDef) { \
> + .misa_mxl_max = (misa_mxl_max_), \
> + }), \
> }
>
> static const TypeInfo riscv_cpu_type_infos[] = {
> --
> 2.49.0
>
next prev parent reply other threads:[~2025-04-06 23:22 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-06 7:02 [PATCH 10.1 v3 00/27] target/riscv: SATP mode and CPU definition overhaul Paolo Bonzini
2025-04-06 7:02 ` [PATCH 01/27] hw/riscv: acpi: only create RHCT MMU entry for supported types Paolo Bonzini
2025-04-06 7:02 ` [PATCH 02/27] target/riscv: assert argument to set_satp_mode_max_supported is valid Paolo Bonzini
2025-04-06 7:02 ` [PATCH 03/27] target/riscv: cpu: store max SATP mode as a single integer Paolo Bonzini
2025-04-06 7:02 ` [PATCH 04/27] target/riscv: update max_satp_mode based on QOM properties Paolo Bonzini
2025-04-06 7:02 ` [PATCH 05/27] target/riscv: remove supported from RISCVSATPMap Paolo Bonzini
2025-04-06 7:02 ` [PATCH 06/27] target/riscv: move satp_mode.{map, init} out of CPUConfig Paolo Bonzini via
2025-04-06 7:02 ` [PATCH 07/27] target/riscv: introduce RISCVCPUDef Paolo Bonzini
2025-04-06 23:21 ` Alistair Francis [this message]
2025-04-06 7:02 ` [PATCH 08/27] target/riscv: store RISCVCPUDef struct directly in the class Paolo Bonzini
2025-04-24 13:52 ` Daniel Henrique Barboza
2025-04-24 14:04 ` Philippe Mathieu-Daudé
2025-04-24 14:21 ` Daniel Henrique Barboza
2025-04-06 7:02 ` [PATCH 09/27] target/riscv: merge riscv_cpu_class_init with the class_base function Paolo Bonzini
2025-04-06 7:02 ` [PATCH 10/27] target/riscv: move RISCVCPUConfig fields to a header file Paolo Bonzini
2025-04-06 7:02 ` [PATCH 11/27] target/riscv: include default value in cpu_cfg_fields.h.inc Paolo Bonzini
2025-04-09 4:53 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 12/27] target/riscv: do not make RISCVCPUConfig fields conditional Paolo Bonzini
2025-04-09 5:12 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 13/27] target/riscv: add more RISCVCPUDef fields Paolo Bonzini
2025-04-22 4:47 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 14/27] target/riscv: convert abstract CPU classes to RISCVCPUDef Paolo Bonzini
2025-04-24 0:50 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 15/27] target/riscv: convert profile CPU models " Paolo Bonzini
2025-04-24 0:11 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 16/27] target/riscv: convert bare " Paolo Bonzini
2025-04-24 0:12 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 17/27] target/riscv: convert dynamic " Paolo Bonzini
2025-04-24 0:15 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 18/27] target/riscv: convert SiFive E " Paolo Bonzini
2025-04-24 0:22 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 19/27] target/riscv: convert ibex " Paolo Bonzini
2025-04-24 0:23 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 20/27] target/riscv: convert SiFive U " Paolo Bonzini
2025-04-24 0:25 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 21/27] target/riscv: th: make CSR insertion test a bit more intuitive Paolo Bonzini
2025-04-24 0:32 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 22/27] target/riscv: generalize custom CSR functionality Paolo Bonzini
2025-04-24 0:36 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 23/27] target/riscv: convert TT C906 to RISCVCPUDef Paolo Bonzini
2025-04-24 0:37 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 24/27] target/riscv: convert TT Ascalon " Paolo Bonzini
2025-04-24 0:38 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 25/27] target/riscv: convert Ventana V1 " Paolo Bonzini
2025-04-24 0:45 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 26/27] target/riscv: convert Xiangshan Nanhu " Paolo Bonzini
2025-04-24 0:47 ` Alistair Francis
2025-04-06 7:02 ` [PATCH 27/27] target/riscv: remove .instance_post_init Paolo Bonzini
2025-04-24 0:48 ` Alistair Francis
2025-04-24 1:26 ` [PATCH 10.1 v3 00/27] target/riscv: SATP mode and CPU definition overhaul Alistair Francis
2025-04-24 14:39 ` Paolo Bonzini
2025-04-25 10:55 ` Paolo Bonzini
2025-04-25 11:02 ` Philippe Mathieu-Daudé
2025-04-25 11:03 ` Paolo Bonzini
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