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Wed, 30 Apr 2025 16:15:46 -0700 (PDT) MIME-Version: 1.0 References: <20250429124421.223883-1-dbarboza@ventanamicro.com> <20250429124421.223883-7-dbarboza@ventanamicro.com> In-Reply-To: <20250429124421.223883-7-dbarboza@ventanamicro.com> From: Alistair Francis Date: Thu, 1 May 2025 09:15:19 +1000 X-Gm-Features: ATxdqUH5C83vX7SCWCF06HGaREtVxI1pY6aSkfYDxp6Ylv1IJVJ-DFVlmSDOEY4 Message-ID: Subject: Re: [PATCH v5 6/9] target/riscv/kvm: do not read unavailable CSRs To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org, ajones@ventanamicro.com, Andrea Bolognani Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::92c; envelope-from=alistair23@gmail.com; helo=mail-ua1-x92c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Apr 29, 2025 at 10:45=E2=80=AFPM Daniel Henrique Barboza wrote: > > [1] reports that commit 4db19d5b21 broke a KVM guest running kernel 6.6. > This happens because the kernel does not know 'senvcfg', making it > unable to boot because QEMU is reading/wriiting it without any checks. > > After converting the CSRs to do "automated" get/put reg procedures in > the previous patch we can now scan for availability. Two functions are > created: > > - kvm_riscv_read_csr_cfg_legacy() will check if the CSR exists by brute > forcing KVM_GET_ONE_REG in each one of them, interpreting an EINVAL > return as indication that the CSR isn't available. This will be use in > absence of KVM_GET_REG_LIST; > > - kvm_riscv_read_csr_cfg() will use the existing result of get_reg_list > to check if the CSRs ids are present. > > kvm_riscv_init_multiext_cfg() is now kvm_riscv_init_cfg() to reflect that > the function is also dealing with CSRs. > > [1] https://lore.kernel.org/qemu-riscv/CABJz62OfUDHYkQ0T3rGHStQprf1c7_E0q= BLbLKhfv=3D+jb0SYAw@mail.gmail.com/ > > Fixes: 4db19d5b21 ("target/riscv/kvm: add missing KVM CSRs") > Reported-by: Andrea Bolognani > Signed-off-by: Daniel Henrique Barboza > Reviewed-by: Andrew Jones Acked-by: Alistair Francis Alistair > --- > target/riscv/kvm/kvm-cpu.c | 62 ++++++++++++++++++++++++++++++++++++-- > 1 file changed, 59 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c > index f881e7eb5d..1ce747d047 100644 > --- a/target/riscv/kvm/kvm-cpu.c > +++ b/target/riscv/kvm/kvm-cpu.c > @@ -636,6 +636,10 @@ static int kvm_riscv_get_regs_csr(CPUState *cs) > for (i =3D 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { > KVMCPUConfig *csr_cfg =3D &kvm_csr_cfgs[i]; > > + if (!csr_cfg->supported) { > + continue; > + } > + > ret =3D kvm_get_one_reg(cs, csr_cfg->kvm_reg_id, ®); > if (ret) { > return ret; > @@ -662,6 +666,10 @@ static int kvm_riscv_put_regs_csr(CPUState *cs) > for (i =3D 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { > KVMCPUConfig *csr_cfg =3D &kvm_csr_cfgs[i]; > > + if (!csr_cfg->supported) { > + continue; > + } > + > if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) =3D=3D sizeof(uint32_t)) { > reg =3D kvm_cpu_csr_get_u32(cpu, csr_cfg); > } else if (KVM_REG_SIZE(csr_cfg->kvm_reg_id) =3D=3D sizeof(uint6= 4_t)) { > @@ -1090,6 +1098,32 @@ static void kvm_riscv_read_multiext_legacy(RISCVCP= U *cpu, > } > } > > +static void kvm_riscv_read_csr_cfg_legacy(KVMScratchCPU *kvmcpu) > +{ > + uint64_t val; > + int i, ret; > + > + for (i =3D 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { > + KVMCPUConfig *csr_cfg =3D &kvm_csr_cfgs[i]; > + struct kvm_one_reg reg; > + > + reg.id =3D csr_cfg->kvm_reg_id; > + reg.addr =3D (uint64_t)&val; > + ret =3D ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); > + if (ret !=3D 0) { > + if (errno =3D=3D EINVAL) { > + csr_cfg->supported =3D false; > + } else { > + error_report("Unable to read KVM CSR %s: %s", > + csr_cfg->name, strerror(errno)); > + exit(EXIT_FAILURE); > + } > + } else { > + csr_cfg->supported =3D true; > + } > + } > +} > + > static int uint64_cmp(const void *a, const void *b) > { > uint64_t val1 =3D *(const uint64_t *)a; > @@ -1146,7 +1180,26 @@ static void kvm_riscv_read_vlenb(RISCVCPU *cpu, KV= MScratchCPU *kvmcpu, > } > } > > -static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kv= mcpu) > +static void kvm_riscv_read_csr_cfg(struct kvm_reg_list *reglist) > +{ > + struct kvm_reg_list *reg_search; > + uint64_t reg_id; > + > + for (int i =3D 0; i < ARRAY_SIZE(kvm_csr_cfgs); i++) { > + KVMCPUConfig *csr_cfg =3D &kvm_csr_cfgs[i]; > + > + reg_id =3D csr_cfg->kvm_reg_id; > + reg_search =3D bsearch(®_id, reglist->reg, reglist->n, > + sizeof(uint64_t), uint64_cmp); > + if (!reg_search) { > + continue; > + } > + > + csr_cfg->supported =3D true; > + } > +} > + > +static void kvm_riscv_init_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) > { > g_autofree struct kvm_reg_list *reglist =3D NULL; > KVMCPUConfig *multi_ext_cfg; > @@ -1163,7 +1216,9 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *c= pu, KVMScratchCPU *kvmcpu) > * (EINVAL). Use read_legacy() in this case. > */ > if (errno =3D=3D EINVAL) { > - return kvm_riscv_read_multiext_legacy(cpu, kvmcpu); > + kvm_riscv_read_multiext_legacy(cpu, kvmcpu); > + kvm_riscv_read_csr_cfg_legacy(kvmcpu); > + return; > } else if (errno !=3D E2BIG) { > /* > * E2BIG is an expected error message for the API since we > @@ -1226,6 +1281,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *c= pu, KVMScratchCPU *kvmcpu) > } > > kvm_riscv_check_sbi_dbcn_support(cpu, reglist); > + kvm_riscv_read_csr_cfg(reglist); > } > > static void riscv_init_kvm_registers(Object *cpu_obj) > @@ -1239,7 +1295,7 @@ static void riscv_init_kvm_registers(Object *cpu_ob= j) > > kvm_riscv_init_machine_ids(cpu, &kvmcpu); > kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); > - kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); > + kvm_riscv_init_cfg(cpu, &kvmcpu); > > kvm_riscv_destroy_scratch_vcpu(&kvmcpu); > } > -- > 2.49.0 > >