[PATCH v3 0/2] hw/riscv: Add fw_cfg support, allow ramfb

[PATCH v3 0/2] hw/riscv: Add fw_cfg support, allow ramfb

[Asherah Connor]

This is version 3 of the series to bring fw_cfg support to riscv's virt
machine, including ramfb support.  It is tested as working against a
modified U-Boot with ramfb support.


Changes in v3:
* Document why fw_cfg is done when it is.
* Move VIRT_FW_CFG before VIRT_FLASH.

Changes in v2:
* Add DMA support (needed for writes).
* Add ramfb as allowed on riscv virt machine class.

Asherah Connor (2):
  hw/riscv: Add fw_cfg support to virt
  hw/riscv: allow ramfb on virt

 hw/riscv/Kconfig        |  1 +
 hw/riscv/virt.c         | 33 +++++++++++++++++++++++++++++++++
 include/hw/riscv/virt.h |  2 ++
 3 files changed, 36 insertions(+)

-- 
2.20.1

[PATCH v3 1/2] hw/riscv: Add fw_cfg support to virt

[Asherah Connor]

Provides fw_cfg for the virt machine on riscv.  This enables
using e.g.  ramfb later.

Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
---

Changes in v3:
* Document why fw_cfg is done when it is.
* Move VIRT_FW_CFG before VIRT_FLASH.

Changes in v2:
* Add DMA support (needed for writes).

 hw/riscv/Kconfig        |  1 +
 hw/riscv/virt.c         | 30 ++++++++++++++++++++++++++++++
 include/hw/riscv/virt.h |  2 ++
 3 files changed, 33 insertions(+)

diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index facb0cbacc..afaa5e58bb 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -33,6 +33,7 @@ config RISCV_VIRT
     select SIFIVE_PLIC
     select SIFIVE_TEST
     select VIRTIO_MMIO
+    select FW_CFG_DMA
 
 config SIFIVE_E
     bool
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 2299b3a6be..82eff42c37 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -56,6 +56,7 @@ static const struct MemmapEntry {
     [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
     [VIRT_UART0] =       { 0x10000000,         0x100 },
     [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
+    [VIRT_FW_CFG] =      { 0x10100000,          0x18 },
     [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
     [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
     [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
@@ -488,6 +489,28 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
     return dev;
 }
 
+static FWCfgState *create_fw_cfg(const RISCVVirtState *s)
+{
+    hwaddr base = virt_memmap[VIRT_FW_CFG].base;
+    hwaddr size = virt_memmap[VIRT_FW_CFG].size;
+    FWCfgState *fw_cfg;
+    char *nodename;
+
+    fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
+                                  &address_space_memory);
+    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)MACHINE(s)->smp.cpus);
+
+    nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
+    qemu_fdt_add_subnode(s->fdt, nodename);
+    qemu_fdt_setprop_string(s->fdt, nodename,
+                            "compatible", "qemu,fw-cfg-mmio");
+    qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg",
+                                 2, base, 2, size);
+    qemu_fdt_setprop(s->fdt, nodename, "dma-coherent", NULL, 0);
+    g_free(nodename);
+    return fw_cfg;
+}
+
 static void virt_machine_init(MachineState *machine)
 {
     const struct MemmapEntry *memmap = virt_memmap;
@@ -652,6 +675,13 @@ static void virt_machine_init(MachineState *machine)
         start_addr = virt_memmap[VIRT_FLASH].base;
     }
 
+    /*
+     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
+     * tree cannot be altered and we get FDT_ERR_NOSPACE.
+     */
+    s->fw_cfg = create_fw_cfg(s);
+    rom_set_fw(s->fw_cfg);
+
     /* Compute the fdt load address in dram */
     fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
                                    machine->ram_size, s->fdt);
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 84b7a3848f..b0ded3fc55 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -40,6 +40,7 @@ struct RISCVVirtState {
     RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
     DeviceState *plic[VIRT_SOCKETS_MAX];
     PFlashCFI01 *flash[2];
+    FWCfgState *fw_cfg;
 
     void *fdt;
     int fdt_size;
@@ -54,6 +55,7 @@ enum {
     VIRT_PLIC,
     VIRT_UART0,
     VIRT_VIRTIO,
+    VIRT_FW_CFG,
     VIRT_FLASH,
     VIRT_DRAM,
     VIRT_PCIE_MMIO,
-- 
2.20.1

Re: [PATCH v3 1/2] hw/riscv: Add fw_cfg support to virt

[Bin Meng]

On Sun, Feb 28, 2021 at 7:17 PM Asherah Connor <ashe@kivikakk.ee> wrote:
>
> Provides fw_cfg for the virt machine on riscv.  This enables
> using e.g.  ramfb later.
>
> Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
> ---
>
> Changes in v3:
> * Document why fw_cfg is done when it is.
> * Move VIRT_FW_CFG before VIRT_FLASH.
>
> Changes in v2:
> * Add DMA support (needed for writes).
>
>  hw/riscv/Kconfig        |  1 +
>  hw/riscv/virt.c         | 30 ++++++++++++++++++++++++++++++
>  include/hw/riscv/virt.h |  2 ++
>  3 files changed, 33 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Re: [PATCH v3 1/2] hw/riscv: Add fw_cfg support to virt

[Alistair Francis]

On Sun, Feb 28, 2021 at 6:45 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Sun, Feb 28, 2021 at 7:17 PM Asherah Connor <ashe@kivikakk.ee> wrote:
> >
> > Provides fw_cfg for the virt machine on riscv.  This enables
> > using e.g.  ramfb later.
> >
> > Signed-off-by: Asherah Connor <ashe@kivikakk.ee>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> > ---
> >
> > Changes in v3:
> > * Document why fw_cfg is done when it is.
> > * Move VIRT_FW_CFG before VIRT_FLASH.
> >
> > Changes in v2:
> > * Add DMA support (needed for writes).
> >
> >  hw/riscv/Kconfig        |  1 +
> >  hw/riscv/virt.c         | 30 ++++++++++++++++++++++++++++++
> >  include/hw/riscv/virt.h |  2 ++
> >  3 files changed, 33 insertions(+)
> >
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
>

Re: [PATCH v3 1/2] hw/riscv: Add fw_cfg support to virt

[Alistair Francis]

On Sun, Feb 28, 2021 at 6:17 AM Asherah Connor <ashe@kivikakk.ee> wrote:
>
> Provides fw_cfg for the virt machine on riscv.  This enables
> using e.g.  ramfb later.
>
> Signed-off-by: Asherah Connor <ashe@kivikakk.ee>

This patch doesn't compile, I see this error:

../hw/riscv/virt.c: In function ‘create_fw_cfg’:
../hw/riscv/virt.c:523:27: error: ‘RISCVVirtState’ has no member named ‘fdt’
 523 |     qemu_fdt_add_subnode(s->fdt, nodename);
     |                           ^~

Can you please fix the compilation failure and send a new version?

Alistair

> ---
>
> Changes in v3:
> * Document why fw_cfg is done when it is.
> * Move VIRT_FW_CFG before VIRT_FLASH.
>
> Changes in v2:
> * Add DMA support (needed for writes).
>
>  hw/riscv/Kconfig        |  1 +
>  hw/riscv/virt.c         | 30 ++++++++++++++++++++++++++++++
>  include/hw/riscv/virt.h |  2 ++
>  3 files changed, 33 insertions(+)
>
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index facb0cbacc..afaa5e58bb 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -33,6 +33,7 @@ config RISCV_VIRT
>      select SIFIVE_PLIC
>      select SIFIVE_TEST
>      select VIRTIO_MMIO
> +    select FW_CFG_DMA
>
>  config SIFIVE_E
>      bool
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 2299b3a6be..82eff42c37 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -56,6 +56,7 @@ static const struct MemmapEntry {
>      [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
>      [VIRT_UART0] =       { 0x10000000,         0x100 },
>      [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
> +    [VIRT_FW_CFG] =      { 0x10100000,          0x18 },
>      [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
>      [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
>      [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
> @@ -488,6 +489,28 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
>      return dev;
>  }
>
> +static FWCfgState *create_fw_cfg(const RISCVVirtState *s)
> +{
> +    hwaddr base = virt_memmap[VIRT_FW_CFG].base;
> +    hwaddr size = virt_memmap[VIRT_FW_CFG].size;
> +    FWCfgState *fw_cfg;
> +    char *nodename;
> +
> +    fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
> +                                  &address_space_memory);
> +    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)MACHINE(s)->smp.cpus);
> +
> +    nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
> +    qemu_fdt_add_subnode(s->fdt, nodename);
> +    qemu_fdt_setprop_string(s->fdt, nodename,
> +                            "compatible", "qemu,fw-cfg-mmio");
> +    qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg",
> +                                 2, base, 2, size);
> +    qemu_fdt_setprop(s->fdt, nodename, "dma-coherent", NULL, 0);
> +    g_free(nodename);
> +    return fw_cfg;
> +}
> +
>  static void virt_machine_init(MachineState *machine)
>  {
>      const struct MemmapEntry *memmap = virt_memmap;
> @@ -652,6 +675,13 @@ static void virt_machine_init(MachineState *machine)
>          start_addr = virt_memmap[VIRT_FLASH].base;
>      }
>
> +    /*
> +     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
> +     * tree cannot be altered and we get FDT_ERR_NOSPACE.
> +     */
> +    s->fw_cfg = create_fw_cfg(s);
> +    rom_set_fw(s->fw_cfg);
> +
>      /* Compute the fdt load address in dram */
>      fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
>                                     machine->ram_size, s->fdt);
> diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
> index 84b7a3848f..b0ded3fc55 100644
> --- a/include/hw/riscv/virt.h
> +++ b/include/hw/riscv/virt.h
> @@ -40,6 +40,7 @@ struct RISCVVirtState {
>      RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
>      DeviceState *plic[VIRT_SOCKETS_MAX];
>      PFlashCFI01 *flash[2];
> +    FWCfgState *fw_cfg;
>
>      void *fdt;
>      int fdt_size;
> @@ -54,6 +55,7 @@ enum {
>      VIRT_PLIC,
>      VIRT_UART0,
>      VIRT_VIRTIO,
> +    VIRT_FW_CFG,
>      VIRT_FLASH,
>      VIRT_DRAM,
>      VIRT_PCIE_MMIO,
> --
> 2.20.1
>
>

Re: [PATCH v3 1/2] hw/riscv: Add fw_cfg support to virt

[Alistair Francis]

On Thu, Mar 18, 2021 at 5:25 PM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Sun, Feb 28, 2021 at 6:17 AM Asherah Connor <ashe@kivikakk.ee> wrote:
> >
> > Provides fw_cfg for the virt machine on riscv.  This enables
> > using e.g.  ramfb later.
> >
> > Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
>
> This patch doesn't compile, I see this error:
>
> ../hw/riscv/virt.c: In function ‘create_fw_cfg’:
> ../hw/riscv/virt.c:523:27: error: ‘RISCVVirtState’ has no member named ‘fdt’
>  523 |     qemu_fdt_add_subnode(s->fdt, nodename);
>      |                           ^~
>
> Can you please fix the compilation failure and send a new version?

I'm guessing the failure is because of "hw/riscv: migrate fdt field to
generic MachineState" which moved the fdt element to the MachineState.

The fix should just be to change s->fdt to mc->fdt.

Sorry that the patch stopped compiling while in the RISC-V tree.

Alistair

>
> Alistair
>
> > ---
> >
> > Changes in v3:
> > * Document why fw_cfg is done when it is.
> > * Move VIRT_FW_CFG before VIRT_FLASH.
> >
> > Changes in v2:
> > * Add DMA support (needed for writes).
> >
> >  hw/riscv/Kconfig        |  1 +
> >  hw/riscv/virt.c         | 30 ++++++++++++++++++++++++++++++
> >  include/hw/riscv/virt.h |  2 ++
> >  3 files changed, 33 insertions(+)
> >
> > diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> > index facb0cbacc..afaa5e58bb 100644
> > --- a/hw/riscv/Kconfig
> > +++ b/hw/riscv/Kconfig
> > @@ -33,6 +33,7 @@ config RISCV_VIRT
> >      select SIFIVE_PLIC
> >      select SIFIVE_TEST
> >      select VIRTIO_MMIO
> > +    select FW_CFG_DMA
> >
> >  config SIFIVE_E
> >      bool
> > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> > index 2299b3a6be..82eff42c37 100644
> > --- a/hw/riscv/virt.c
> > +++ b/hw/riscv/virt.c
> > @@ -56,6 +56,7 @@ static const struct MemmapEntry {
> >      [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
> >      [VIRT_UART0] =       { 0x10000000,         0x100 },
> >      [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
> > +    [VIRT_FW_CFG] =      { 0x10100000,          0x18 },
> >      [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
> >      [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
> >      [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
> > @@ -488,6 +489,28 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
> >      return dev;
> >  }
> >
> > +static FWCfgState *create_fw_cfg(const RISCVVirtState *s)
> > +{
> > +    hwaddr base = virt_memmap[VIRT_FW_CFG].base;
> > +    hwaddr size = virt_memmap[VIRT_FW_CFG].size;
> > +    FWCfgState *fw_cfg;
> > +    char *nodename;
> > +
> > +    fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
> > +                                  &address_space_memory);
> > +    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)MACHINE(s)->smp.cpus);
> > +
> > +    nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
> > +    qemu_fdt_add_subnode(s->fdt, nodename);
> > +    qemu_fdt_setprop_string(s->fdt, nodename,
> > +                            "compatible", "qemu,fw-cfg-mmio");
> > +    qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg",
> > +                                 2, base, 2, size);
> > +    qemu_fdt_setprop(s->fdt, nodename, "dma-coherent", NULL, 0);
> > +    g_free(nodename);
> > +    return fw_cfg;
> > +}
> > +
> >  static void virt_machine_init(MachineState *machine)
> >  {
> >      const struct MemmapEntry *memmap = virt_memmap;
> > @@ -652,6 +675,13 @@ static void virt_machine_init(MachineState *machine)
> >          start_addr = virt_memmap[VIRT_FLASH].base;
> >      }
> >
> > +    /*
> > +     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
> > +     * tree cannot be altered and we get FDT_ERR_NOSPACE.
> > +     */
> > +    s->fw_cfg = create_fw_cfg(s);
> > +    rom_set_fw(s->fw_cfg);
> > +
> >      /* Compute the fdt load address in dram */
> >      fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
> >                                     machine->ram_size, s->fdt);
> > diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
> > index 84b7a3848f..b0ded3fc55 100644
> > --- a/include/hw/riscv/virt.h
> > +++ b/include/hw/riscv/virt.h
> > @@ -40,6 +40,7 @@ struct RISCVVirtState {
> >      RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
> >      DeviceState *plic[VIRT_SOCKETS_MAX];
> >      PFlashCFI01 *flash[2];
> > +    FWCfgState *fw_cfg;
> >
> >      void *fdt;
> >      int fdt_size;
> > @@ -54,6 +55,7 @@ enum {
> >      VIRT_PLIC,
> >      VIRT_UART0,
> >      VIRT_VIRTIO,
> > +    VIRT_FW_CFG,
> >      VIRT_FLASH,
> >      VIRT_DRAM,
> >      VIRT_PCIE_MMIO,
> > --
> > 2.20.1
> >
> >

Re: [PATCH v3 1/2] hw/riscv: Add fw_cfg support to virt

[Asherah Connor]

Hi Alistair,

On 21/03/18 05:03:p, Alistair Francis wrote:
> I'm guessing the failure is because of "hw/riscv: migrate fdt field to
> generic MachineState" which moved the fdt element to the MachineState.
> 
> The fix should just be to change s->fdt to mc->fdt.

Yes, looks like it.  I'll fix it up and retest locally before sending
out the new version.

> Sorry that the patch stopped compiling while in the RISC-V tree.

On the contrary, thanks for bringing it to my attention.

Best,

Asherah

[PATCH v3 2/2] hw/riscv: allow ramfb on virt

[Asherah Connor]

Allow ramfb on virt.  This lets `-device ramfb' work.

Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

---

(no changes since v2)

Changes in v2:
* Add ramfb as allowed on riscv virt machine class.

 hw/riscv/virt.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 82eff42c37..700b481fa2 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -42,6 +42,7 @@
 #include "sysemu/sysemu.h"
 #include "hw/pci/pci.h"
 #include "hw/pci-host/gpex.h"
+#include "hw/display/ramfb.h"
 
 static const struct MemmapEntry {
     hwaddr base;
@@ -743,6 +744,8 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
     mc->numa_mem_supported = true;
+
+    machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
 }
 
 static const TypeInfo virt_machine_typeinfo = {
-- 
2.20.1

Re: [PATCH v3 2/2] hw/riscv: allow ramfb on virt

[Alistair Francis]

On Sun, Feb 28, 2021 at 6:20 AM Asherah Connor <ashe@kivikakk.ee> wrote:
>
> Allow ramfb on virt.  This lets `-device ramfb' work.
>
> Signed-off-by: Asherah Connor <ashe@kivikakk.ee>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

>
> ---
>
> (no changes since v2)
>
> Changes in v2:
> * Add ramfb as allowed on riscv virt machine class.
>
>  hw/riscv/virt.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 82eff42c37..700b481fa2 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -42,6 +42,7 @@
>  #include "sysemu/sysemu.h"
>  #include "hw/pci/pci.h"
>  #include "hw/pci-host/gpex.h"
> +#include "hw/display/ramfb.h"
>
>  static const struct MemmapEntry {
>      hwaddr base;
> @@ -743,6 +744,8 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
>      mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
>      mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
>      mc->numa_mem_supported = true;
> +
> +    machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
>  }
>
>  static const TypeInfo virt_machine_typeinfo = {
> --
> 2.20.1
>
>

Re: [PATCH v3 0/2] hw/riscv: Add fw_cfg support, allow ramfb

[Alistair Francis]

On Sun, Feb 28, 2021 at 6:18 AM Asherah Connor <ashe@kivikakk.ee> wrote:
>
> This is version 3 of the series to bring fw_cfg support to riscv's virt
> machine, including ramfb support.  It is tested as working against a
> modified U-Boot with ramfb support.

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>
> Changes in v3:
> * Document why fw_cfg is done when it is.
> * Move VIRT_FW_CFG before VIRT_FLASH.
>
> Changes in v2:
> * Add DMA support (needed for writes).
> * Add ramfb as allowed on riscv virt machine class.
>
> Asherah Connor (2):
>   hw/riscv: Add fw_cfg support to virt
>   hw/riscv: allow ramfb on virt
>
>  hw/riscv/Kconfig        |  1 +
>  hw/riscv/virt.c         | 33 +++++++++++++++++++++++++++++++++
>  include/hw/riscv/virt.h |  2 ++
>  3 files changed, 36 insertions(+)
>
> --
> 2.20.1
>
>