Re: [PATCH qemu v2] target/riscv: Check ext_zca for misaligned return address of mret/sret.

[Alistair Francis <alistair23@gmail.com>]

On Mon, Feb 3, 2025 at 3:34 PM ~yuming <yuming@git.sr.ht> wrote:
>
> From: Yu-Ming Chang <yumin686@andestech.com>
>
> We only check RVC to allow 16-bit aligned return addreses. This will
> cause issues when only ext_zca is enabled without RVC: 16-bit
> instructions are allowed, but 16-bit aligned return address are not.
> We should also check ext_zca to permit 16-bit aligned return addresses.
>
> Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
> ---
> The v2 has been updated to provide more explanation.
>
>  target/riscv/op_helper.c | 12 ++++++++----
>  1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index eddedacf4b..891002f954 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -269,8 +269,10 @@ target_ulong helper_sret(CPURISCVState *env)
>      }
>
>      target_ulong retpc = env->sepc;
> -    if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
> -        riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> +    if (!riscv_has_ext(env, RVC) && !env_archcpu(env)->cfg.ext_zca) {

You can just check ext_zca as C always implies Zca

Alistair

> +        if ((retpc & 0x3) != 0) {
> +            riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> +        }
>      }
>
>      if (get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) {
> @@ -328,8 +330,10 @@ target_ulong helper_mret(CPURISCVState *env)
>      }
>
>      target_ulong retpc = env->mepc;
> -    if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
> -        riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> +    if (!riscv_has_ext(env, RVC) && !env_archcpu(env)->cfg.ext_zca) {
> +        if ((retpc & 0x3) != 0) {
> +            riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> +        }
>      }
>
>      uint64_t mstatus = env->mstatus;
> --
> 2.45.3
>